|
|
|
부품번호 | W184-5 기능 |
|
|
기능 | Six Output Peak Reducing EMI Solution | ||
제조업체 | Cypress Semiconductor | ||
로고 | |||
전체 8 페이지수
W184
Six Output Peak Reducing EMI Solution
Features
Table 1. Modulation Width Selection
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable input to output frequency
• Six 1.25%, 3.75%, or 0% down or center spread outputs
• One non-Spread reference output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
• Available in 24-pin SSOP (Shrunk Small Outline
Package)
• Outputs may be selectively disabled
Key Specifications
Supply Voltages: ........................................... VDD = 3.3V±5%
or VDD = 5V±10%
Frequency Range: .............................. 8 MHz ≤ Fin ≤ 28 MHz
Crystal Reference Range.................... 8 MHz ≤ Fin ≤ 28 MHz
Cycle to Cycle Jitter: ........................................ 300 ps (max.)
Selectable Spread Percentage: ....................1.25% or 3.75%
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time: .................................. 5 ns (max.)
SS%
0
1
W184
Output
Fin ≥ Fout ≥ Fin – 1.25%
Fin ≥ Fout ≥ Fin – 3.75%
W184-5
Output
Fin + 0.625% ≥ Fin≥ –
0.625%
Fin + 1.875% ≥ Fin≥
–1.875%
Table 2. Frequency Range Selection
FS2 FS1
00
01
10
11
Table 3. Output Enable
Frequency Range
8 MHz ≤ FIN ≤ 10 MHz
10 MHz ≤ FIN ≤ 15 MHz
15 MHz ≤ FIN ≤ 18 MHz
18 MHz ≤ FIN ≤ 28 MHz
EN1
0
0
1
EN2
0
1
0
CLK0:4
Low
Low
Active
CLK5
Low
Active
Low
1 1 Active
Active
Simplified Block Diagram
3.3 or 5.0V
XTAL
Input
X1
X2
W184
Spread Spectrum
Outputs
(EMI suppressed)
3.3 or 5.0V
Oscillator or
Reference Input
W184
Spread Spectrum
Outputs
(EMI suppressed)
Pin Configuration
SSOP
REFOUT
FS2
X1
X2
GND
SS%
EN2
GND
CLK0
VDD
CLK1
CLK2
1
2
3
4
5
6
7
8
9
10
11
12
24 SSON#
23 RESET
22 FS1
21 VDD
20 VDD
19 NC
18 EN1
17 CLK5
16 VDD
15 CLK4
14 GND
13 CLK3
PREMIS is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 25, 2000, rev. *B
W184
Spread Spectrum Frequency Timing
Generation
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in )LJXUH .
As shown in )LJXUH , a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log10(P) + 9*log10(F)
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
)LJXUH . This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. )LJXUH
details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
SSFTG
Typical Clock
EMI Reduction
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Frequency Span (MHz)
Center Spread
Frequency Span (MHz)
Down Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 3. Typical Modulation Profile
4
4페이지 W184
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
VDD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the VDD pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the VDD connection can be
made via a ferrite bead, as shown.
Clock Output
R1
Logic Input
Reference Input
XTAL connection or NC
Clock Output
Clock Output
Clock Output
Logic Input
Logic Input
R1
R1
R1
1
2
3
4
5
6
7
8
9
10
11
12
C1
0.1 µF
24 Logic Input
23 Logic Input
22 Logic Input
21
20
19 NC
18 Logic Input
17
16 R1
15
14 R1
13
R1
C1
0.1 µF
Clock Output
Clock Output
Clock Output
C1
0.1 µF
C1
0.1 µF
FB
3.3 or 5V System Supply
C2
10-µF Tantalum
Figure 4. Recommended Circuit Configuration
Ordering Information
Ordering Code
Package
Name
W184
W184-5
H
Package Type
24-Pin SSOP (209-mil)
Document #: 38-00797-B
7
7페이지 | |||
구 성 | 총 8 페이지수 | ||
다운로드 | [ W184-5.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
W184-5 | Six Output Peak Reducing EMI Solution | Cypress Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |