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W196 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 W196은 전자 산업 및 응용 분야에서
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부품번호 W196 기능
기능 Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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W196 데이터시트, 핀배열, 회로
PRELIMINARY
W196
Spread Spectrum FTG for 440BX and VIA Apollo Pro-133
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• System frequency synthesizer for 440BX, 440ZX, and
VIA Apollo Pro-133
• I2C programmable to 155 MHz (32 selectable
frequencies)
• Two skew-controlled copies of CPU output
• Seven copies of PCI output (synchronous w/CPU out-
put)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz clock is determined by resistor
straps on power up
• One high-drive output buffer that produces a copy of
the 14.318-MHz reference
• Isolated core VDD pin for noise reduction
Key Specifications
Supply Voltages: ....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
VDDQ3
REF2X/SEL48#
GND
VDDQ3
IOAPIC
FS1 PLL 1
FS0
÷2/÷3
SDATA
SCLOCK
I2C
LOGIC
VDDQ2
CPU0
CPU1
GND
VDDQ3
PCI_F
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
GND
CPU Cycle to Cycle Jitter: .......................................... 250 ps
CPU, PCI Output Edge Rate: ......................................... ≥1 V/ns
CPU0:1 Output Skew: ................................................ 175 ps
PCI_F, PCI1:6 Output Skew: .......................................500 ps
CPU to PCI Skew: ........................ 1.5 to 4.0 ns (CPU Leads)
REF2X/SEL48#, SCLOCK, SDATA: ............... 250-kpull-up
FS1: ............................................................250-kpull-down
FS0: ...................................................No pull-up or pull-down
Note: Internal pull-up or pull-down resistors should not be re-
lied upon for setting I/O pins HIGH or LOW.
Table 1. Pin Selectable Frequency
FS1 FS0 CPU(0:1) PCI
1 1 133.3 MHz 33.3 MHz
1
0
105 MHz
35 MHz
0
1
100 MHz
33.3 MHz
0 0 66.8 MHz 33.3 MHz
Pin Configuration
X1
X2
GND
PCI_F
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
PCI6
VDDQ3
48MHz
24_48MHz/FS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 GND
27 REF2X/SEL48#
26 VDDQ3
25 VDDQ2
24 IOAPIC
23 VDDQ2
22 CPU0
21 CPU1
20 VDDQ3
19 GND
18 SDATA
17 SCLOCK
16 FS0
15 GND
PLL2
VDDQ3
48MHz
24_48MHz/FS1
GND
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 28, 1999, rev. **




W196 pdf, 반도체, 판매, 대치품
PRELIMINARY
W196
Serial Data Interface
The W196 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W196 initializes with
default register settings. Therefore, the use of this serial data
interface is optional. The serial interface is write-only (to the
clock chip) and is the dedicated function of device pins SDATA
and SCLOCK. In motherboard applications, SDATA and
SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if required. The interface can also
be used during system operation for power management func-
tions. Table 2 summarizes the control functions of the serial
data interface.
Operation
Data is written to the W196 in ten bytes of eight bits each.
Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI and
system power. Examples are clock outputs to un-
used PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond
the selections that are provided by the FS0:1 pins.
Frequency is changed in a smooth and controlled
fashion.
For alternate microprocessors and power man-
agement options. Smooth frequency transition al-
lows CPU frequency change under normal system
operation.
Output Three-state Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode
All clock outputs toggle in relation to X1 input, in- Production PCB testing.
ternal PLL is bypassed. Refer to Table 4.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be written
duction device testing.
as 0.
Table 3. Byte Writing Sequence
Byte
Sequence
Byte Name
Bit Sequence
1 Slave Address 11010010
2 Command Dont Care
Code
3
Byte Count
Dont Care
4
Data Byte 0
Dont Care
5 Data Byte 1
6 Data Byte 2
7
Data Byte 3
Refer to Table 4
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
Byte Description
Commands the W196 to accept the bits in Data Bytes 36 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W196 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W196, therefore bit values are ignored (dont care). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial com-
munication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
Unused by the W196, therefore bit values are ignored (dont care). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
Refer to Cypress SDRAM drivers.
The data bits in these bytes set internal W196 registers that control device
operation. The data bits are only accepted when the Address Byte bit
sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 4, Data Byte Serial Configuration Map.
4

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W196 전자부품, 판매, 대치품
PRELIMINARY
W196
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Parameter
VDD, VIN
TSTG
TA
TB
ESDPROT
Description
Voltage on any pin with respect to GND
Storage Temperature
Operating Temperature
Ambient Temperature under Bias
Input ESD Protection
Rating
0.5 to +7.0
65 to +150
0 to +70
55 to +125
2 (min.)
Unit
V
°C
°C
°C
kV
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max. Unit
Supply Current
IDDQ3
Combined 3.3V Supply Current
CPU0:1 =100 MHz
Outputs Loaded[3]
85 mA
IDDQ3
Combined 2.5V Supply Current
CPU0:1 =100 MHz
Outputs Loaded[3]
30 mA
Logic Inputs
VIL Input Low Voltage
VIH Input High Voltage
IIL Input Low Current[4]
IIH Input High Current[4]
Clock Outputs
GND 0.3
2.0
0.8
VDD + 0.3
25
10
V
V
µA
µA
VOL Output Low Voltage
IOL = 1 mA
50 mV
VOH Output High Voltage
IOH = 1 mA
3.1
V
VOH Output High Voltage CPU0:1/IOAPIC IOH = 1 mA
2.2
V
IOL
Output Low Current CPU0:1
VOL = 1.25V
45 60 80 mA
PCI_F, PCI1:6 VOL = 1.5V
85 110 140 mA
IOAPIC
VOL = 1.25V
65 90 140 mA
REF2X
VOL = 1.5V
110 140 170 mA
48MHz, 24MHz VOL = 1.5V
50 70 90 mA
IOH
Output High Current CPU0:1
VOL = 1.25V
35 50 80 mA
PCI_F, PCI1:6 VOL = 1.5V
60 95 130 mA
IOAPIC
VOL = 1.25V
45 87 140 mA
REF2X
VOL = 1.5V
100 130 150 mA
48MHz, 24MHz VOL = 1.5V
50 70 90 mA
Crystal Oscillator
VTH X1 Input Threshold Voltage[5]
VDDQ3 = 3.3V
1.65 V
CLOAD
Load Capacitance, as seen by
External Crystal[6]
14 pF
CIN,X1
X1 Input Capacitance[7]
Pin X2 unconnected
28 pF
Notes:
3. All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section.
4. W196 logic inputs have internal pull-up resistors, except SEL100/66# (pull-ups not full CMOS level).
5. X1 input threshold voltage (typical) is VDD/2.
6. The W196 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
14 pF; this includes typical stray capacitance of short PCB traces to crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
7

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