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W24258Q-70LI 데이터시트 PDF




Winbond에서 제조한 전자 부품 W24258Q-70LI은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 W24258Q-70LI 기능
기능 32K X 8 CMOS STATIC RAM
제조업체 Winbond
로고 Winbond 로고


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W24258Q-70LI 데이터시트, 핀배열, 회로
W24258
32K × 8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24258 is a normal speed, very low power CMOS static RAM organized as 32768 × 8 bits that
operates on a wide voltage range from 2.7V to 5.5V power supply. The W24258 family, W24258-
70LE and W24258-70LI, can meet requirement of various operating temperature. This device is
manufactured using Winbond's high performance CMOS technology.
FEATURES
Low power consumption:
Active: 350 mW (max.)
Standby: 6 µW (max.)/3V
25 µW (max.)/5V
Access time: 70 nS (max.)/5V
100 nS (max.)/3V
Single 3V/5V power supply
Fully static operation
All inputs and outputs directly TTL compatible
Three-state outputs
Battery back-up operation capability
Data retention voltage: 2V (min.)
Packaged in 28-pin 600 mil DIP, 330 mil SOP
and standard type one TSOP (8 mm × 13.4
mm)
PIN CONFIGURATIONS
BLOCK DIAGRAM
A14 1
28
A12 2
27
A7 3
26
A6 4
25
A5 5
24
A4 6
A3 7
23
28-pin
DIP 22
A2 8
21
A1 9
20
A0 10
19
I/O1 11
18
I/O2 12
17
I/O3
VSS
13
14
16
15
VDD
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
OE 1
A11 2
A9 3
A8 4
A13 5
WE 6
VDD 7
A14 8
A12 9
A7 1
A6 0
A5 1
A4 1
A3 1
2
28-pin
TSOP
28 A10
27 CS
26 I/O8
25 I/O7
24 I/O6
23 I/O5
22 I/O4
21 VSS
20 I/O3
19 I/O2
18 I/O1
17 A0
16 A1
15 A2
CLK GEN.
PRECHARGE CKT.
A12
A14
R
A2 O
W CORE CELL ARRAY
A3
A4
D
E
512 ROWS
A5
C
O
64 X 8 COLUMNS
D
A6 E
R
A7
A13
I/O1 DATA
I/O CKT.
I/O8 CNTRL. COLUMN DECODER
CLK
GEN.
A11 A10 A1 A0 A8 A9
WE
CS
OE
PIN DESCRIPTION
SYMBOL
A0A14
I/O1I/O8
CS
WE
OE
VDD
VSS
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input
Power Supply
Ground
Publication Release Date: November 1998
- 1 - Revision A8




W24258Q-70LI pdf, 반도체, 판매, 대치품
W24258
AC Characteristics, continued
(VDD = 5V ±10%; VDD = 3V ±10%; VSS = 0V; TA (°C) = -20 to 85 for LE; -40 to 85 for LI)
Read Cycle
PARAMETER
SYM.
Read Cycle Time
TRC
Address Access Time
TAA
Chip Select Access Time
TACS
Output Enable to Output Valid
TAOE
Chip Selection to Output in Low Z
TCLZ*
Output Enable to Output in Low Z
TOLZ*
Chip Deselection to Output in High Z TCHZ*
Output Disable to Output in High Z
TOHZ*
Output Hold from Address Change
TOH
These parameters are sampled but not 100% tested
5V
MIN. MAX.
70 -
- 70
- 70
- 35
10 -
5-
- 30
- 30
10 -
3V
MIN. MAX.
100 -
- 100
- 100
- 50
15 -
5-
- 35
- 35
15 -
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
Write Cycle
PARAMETER
SYM.
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
CS, WE
Data Valid to End of Write
Data Hold from End of Write
Write to Output in High Z
Output Disable to Output in High Z
Output Active from End of Write
TWC
TCW
TAW
TAS
TWP
TWR
TDW
TDH
TWHZ*
TOHZ*
TOW
These parameters are sampled but not 100% tested
5V
MIN. MAX.
70 -
50 -
50 -
0-
50 -
0-
30 -
0-
- 25
- 25
5-
3V
MIN.
MAX.
100 -
70 -
70 -
0-
70 -
0-
50 -
0-
- 30
- 30
10 -
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
-4-

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W24258Q-70LI 전자부품, 판매, 대치품
W24258
DATA RETENTION CHARACTERISTICS
(TA (°C) =-20 to 85 for LE; -40 to 85 for LI)
PARAMETER
SYM.
TEST CONDITIONS
VDD for Data Retention
VDR CS VDD -0.2V
Data Retention Current
IDDDR CS VDD -0.2V, VDD = 3V
Chip Deselect to Data
Retention Time
TCDR See data retention waveform
Operation Recovery Time TR
* Read Cycle Time
MIN. TYP. MAX. UNIT
2.0 - - V
- - 2 µA
0 - - nS
TRC* -
- nS
DATA RETENTION WAVEFORM
VDD
0.9 VDD
TCDR
VDR => 2V
0.9VDD
TR
CS
VIH
CS => VDD - 0.2V
VIH
ORDERING INFORMATION
PART NO.
ACCESS OPERATING
OPERATING
TIME (nS) VOLTAGE (V) TEMPERATURE (°C)
PACKAGE
W24258H
100 3V
0 to 70
Die form
W24258-70LE
70/100
5V/3V
-20 to 85
600 mil DIP
W24258S-70LE
70/100
5V/3V
-20 to 85
330 mil SOP
W24258Q-70LE 70/100
5V/3V
-20 to 85
Standard type one TSOP
W24258-70LI
70/100
5V/3V
-40 to 85
600 mil DIP
W24258S-70LI
70/100
5V/3V
-40 to 85
330 mil SOP
W24258Q-70LI
70/100
5V/3V
-40 to 85
Standard type one TSOP
Notes:
1. Winbond reserves the right to make changes to its products without prior notice.
2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications
where personal injury might occur as a consequence of product failure.
Publication Release Date: November 1998
- 7 - Revision A8

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