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W29C040 데이터시트 PDF




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부품번호 W29C040 기능
기능 512K X 8 CMOS FLASH MEMORY
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W29C040 데이터시트, 핀배열, 회로
W29C040
512K × 8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W29C040 is a 4-megabit, 5-volt only CMOS page mode EEPROM organized as 512K × 8 bits.
The device can be written (erased and programmed) in-system with a standard 5V power supply. A
12-volt VPP is not required. The unique cell architecture of the W29C040 results in fast write (erase/
program) operations with extremely low current consumption compared to other comparable 5-volt
flash memory products. The device can also be written (erased and programmed) by using standard
EPROM programmers.
FEATURES
Single 5-volt write (erase and program)
operations
Fast page-write operations
256 bytes per page
Page write (erase/program) cycle: 5 mS
(typ.)
Effective byte-write (erase/program) cycle
time: 19.5 µS
Optional software-protected data write
Fast chip-erase operation: 50 mS
Two 16 KB boot blocks with lockout
Typical page write (erase/program) cycles:
1K/10K (typ.)
Read access time: 90/120 nS
Ten-year data retention
Software and hardware data protection
Low power consumption
Active current: 25 mA (typ.)
Standby current: 20 µA (typ.)
Automatic write (erase/program) timing with
internal VPP generation
End of write (erase/program) detection
Toggle bit
Data polling
Latched address and data
All inputs and outputs directly TTL compatible
JEDEC standard byte-wide pinouts
Available packages: TSOP and PLCC
Publication Release Date: May 1999
- 1 - Revision A5




W29C040 pdf, 반도체, 판매, 대치품
W29C040
will remain enabled unless the disable commands are issued. A power transition will not reset the
software
data protection feature. To reset the device to unprotected mode, a six byte command sequence is
required. For information about specific codes, see the Command Codes for Software Data
Protection in the Table of Operating Modes. For information about timing waveforms, see the timing
diagrams below.
Hardware Data Protection
The integrity of the data stored in the W29C040 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VCC Power Up/Down Detection: The write operation is inhibited when VCC is less than 2.5V.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) VCC power-on delay: When VCC has reach its sense level, the device will automatically time-out
10 mS before any write (erase/program) operation.
Chip Erase Modes
The entire device can be erased by using a six-byte software command code. See the Software Chip
Erase Timing Diagram.
Boot Block Operation
There are two boot blocks (16K bytes each) in this device, which can be used to store boot code. One
of them is located in the first 16K bytes and the other is located in the last 16K bytes of the memory.
The first 16K or last 16K of the memory can be set as a boot block by using a seven-byte command
sequence.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set
the data for the designated block cannot be erased or programmed (programming lockout); other
memory locations can be changed by the regular programming method. Once the boot block
programming lockout feature is activated, the chip erase function will be disabled. In order to detect
whether the boot block feature is set on the two 16K blocks, users can perform a six-byte command
sequence: enter the product identification mode (see Command Codes for Identification/Boot Block
Lockout Detection for specific code), and then read from address "00002 hex" (for the first 16K bytes)
or "7FFF2 hex" (for the last 16K bytes). If the output data is "FF hex," the boot block programming
lockout feature is activated; if the output data is "FE hex," the lockout feature is inactivated and the
block can be programmed.
To return to normal operation, perform a three-byte command sequence to exit the identification
mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Data Polling (DQ7)- Write Status Detection
The W29C040 includes a data polling feature to indicate the end of a write cycle. When the
W29C040 is in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the
page/byte-load cycle will receive the complement of the true data. Once the write cycle is completed.
DQ7 will show the true data. See the DATA Polling Timing Diagram.
-4-

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W29C040 전자부품, 판매, 대치품
Command Codes for Software Chip Erase
BYTE SEQUENCE
0 Write
1 Write
2 Write
3 Write
4 Write
5 Write
ADDRESS
5555H
2AAAH
5555H
5555H
2AAAH
5555H
Software Chip Erase Acquisition Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 80
to
address 5555
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data 10
to
address 5555
Pause 50 mS
Notes for software chip erase:
Data Format: DQ7DQ0 (Hex)
Address Format: A14A0 (Hex)
Exit
-7-
W29C040
DATA
AAH
55H
80H
AAH
55H
10H
Publication Release Date: May 1999
Revision A5

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W29C040

512K X 8 CMOS FLASH MEMORY

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