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W49F201 데이터시트 PDF




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부품번호 W49F201 기능
기능 128K X 16 CMOS FLASH MEMORY
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W49F201 데이터시트, 핀배열, 회로
Preliminary W49F201
128K × 16 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W49F201 is a 2-megabit, 5-volt only CMOS flash memory organized as 128K × 16 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49F201 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
Single 5-volt operations:
5-volt Read/Erase/Program
Fast Program operation:
Word-by-Word programming: 50 µS (max.)
Fast Erase operation: 60 mS (typ.)
Fast Read access time: 45/55 nS
Endurance: 1K/10K cycles (typ.)
Ten-year data retention
Hardware data protection
Sector configuration
One 8K words boot block with lockout
protection
Two 8K words parameter blocks
One 104K words (208K bytes) Main Memory
Array Blocks
Low power consumption
Active current: 25 mA (typ.)
Standby current: 20 µA (typ.)
Automatic program and erase timing with
internal VPP generation
End of program or erase detection
Toggle bit
Data polling
Latched address and data
TTL compatible I/O
JEDEC standard word-wide pinouts
Available packages: 44-pin SOP, 48-pin TSOP
Publication Release Date: June 1999
- 1 - Revision A1




W49F201 pdf, 반도체, 판매, 대치품
Preliminary W49F201
completed in a fast 100 mS (typical). The host system is not required to provide any control or timing
during this operation. The entire memory array will be erased to FF(hex). by the chip erase operation
if the boot block programming lockout feature is not activated. Once the boot block lockout feature is
activated, the chip erase function will erase all the sectors except the boot mode.
Sector Erase Operation
The three sectors, main memory and two parameters blocks, can be erased individually by initiating a
six-word command sequence. Sector address is latched on the falling WE edge of the sixth cycle
while the 30(hex) data input command is latched at the rising edge of WE. After the command
loading cycle, the device enters the internal sector erase mode, which is automatically timed and will
be completed in a fast 100 mS (typical). The host system is not required to provide any control or
timing during this operation. The device will automatically return to normal read mode after the erase
operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
When the boot block lockout feature is inactivated, the boot block and the main memory block will be
erased together. Once the boot block is locked, only the main memory block will be erased by the
execution of sector erase operation.
Program Operation
The W49F201 is programmed on a word-by-word basis. Program operation can only change logical
data "1" to logical data "0" The erase operation (changed entire data in main memory and/or boot
block from "0" to "1" is needed before programming.
The program operation is initiated by a 4-word command cycle (see Command Codes for Word
Programming). The device will internally enter the program operation immediately after the word-
program command is entered. The internal program timer will automatically time-out (50 µS max. -
TBP) once completed and return to normal read mode. Data polling and/or Toggle Bits can be used to
detect end of program cycle.
Hardware Data Protection
The integrity of the data stored in the W49F201 is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) VDD Power Up/Down Detection: The programming operation is inhibited when VDD is less than
2.5V typical.
(3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This
prevents inadvertent writes during power-up or power-down periods.
(4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out
5 mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W49F201 includes a data polling feature to indicate the end of a program or erase cycle. When
the W49F201 is in the internal program or erase cycle, any attempt to read DQ7 of the last word
loaded will receive the complement of the true data. Once the program or erase cycle is completed,
DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and become
logical "1" or true data when the erase cycle has been completed.
-4-

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W49F201 전자부품, 판매, 대치품
Preliminary W49F201
Command Codes for Word Program
WORD SEQUENCE
0 Write
1 Write
2 Write
3 Write
ADDRESS
DATA
5555H
AAH
2AAAH
55H
5555H
A0H
Programmed-address
Programmed-data
Pause 50 µS
Word Program Flow Chart
Word Program
Command Flow
Load data AA
to
address 5555
Load data 55
to
address 2AAA
Load data A0
to
address 5555
Load data Din
to
programmed-
address
Pause 50 µS
Exit
Notes for software program code:
Data Format: DQ15DQ8: Don't Care; DQ7-DQ0 (Hex)
Address Format: A14A0 (Hex)
*It is not allowed to assert read command during the 4-word command sequence(program).
To assert the read command during the 4-word command sequence will abort programming procedure.
Publication Release Date: June 1999
- 7 - Revision A1

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