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W78L51F-24 데이터시트 PDF




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기능 8-BIT MICROCONTROLLER
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W78L51F-24 데이터시트, 핀배열, 회로
W78L51
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78L51 microcontroller supplies a wider frequency and supply voltage range than most 8-bit
microcontrollers on the market. It is compatible with the industry standard 80C51 microcontroller
series.
The W78L51 contains four 8-bit bidirectional parallel ports, one extra 4-bit bit-addressable I/O port
(Port 4) and two additional external interrupts (INT2 , INT3 ), two 16-bit timer/counters, one watchdog
timer and a serial port. These peripherals are supported by a seven-source, two-level interrupt
capability. There are 128 bytes of RAM and an 4K byte mask ROM for application programs.
The W78L51 microcontroller has two power reduction modes, idle mode and power-down mode, both
of which are software selectable. The idle mode turns off the processor clock but allows for continued
peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
Fully static design
Supply voltage of 1.8V to 5.5V
DC-24 MHz operation
128 bytes of on-chip scratchpad RAM
4K bytes of on-chip mask ROM
64K bytes program memory address space
64K bytes data memory address space
Four 8-bit bidirectional ports
Two 16-bit timer/counters
One full duplex serial port
Seven-source, two-level interrupt capability
One extra 4-bit bit-addressable I/O port
Two additional external interrupts INT2 / INT3
Watchdog timer
EMI reduction mode
Built-in power management
Code protection
Packages:
DIP 40: W78L51-24
PLCC 44: W78L51P-24
QFP 44: W78L51F-24
Publication Release Date: January 1999
- 1 - Revision A2




W78L51F-24 pdf, 반도체, 판매, 대치품
W78L51
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high impedance state during reset with
a weak pull-up.
PSEN
Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0
address/data bus during fetch and MOVC operations. PSEN goes to a high impedance state during
reset with a weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VDD
Power Supplies. These are the chip ground and positive supplies.
BLOCK DIAGRAM
P1.0
~
P1.7
Port
1
INT2
INT3
P3.0
~
P3.7
Port
3
P4.0
~
P4.3
Port
4
Port 1
Latch
Interrupt
Timer
0
Timer
1
UART
ACC
T1
B
T2
PSW
Stack
ALU Pointer
Port 0
Latch
DPTR
Temp Reg.
PC
Incrementor
Addr. Reg.
Port 3
Latch
Instruction
Decoder
&
Sequencer
SFR RAM
Address
128bytes
RAM & SFR
Port 4
Latch
Bus & Clock
Controller
4KB
ROM
Watchdog
Timer
Oscillator
Reset Block
Power control
Port 2
Latch
XTAL1 XTAL2 ALE PSEN RST
VDD GND
P0.0
Port
0
~
P0.7
P2.0
Port
2
~
P2.7
-4-

4페이지










W78L51F-24 전자부품, 판매, 대치품
W78L51
2. PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2 /
INT3 ).
Example: P4
REG 0D8H
MOV P4, #0AH ; Output data "A" through P4.0P4.3.
MOV A, P4
; Read P4 status to Accumulator.
SETB P4.0
; Set bit P4.0
CLR P4.1
; Clear bit P4.1
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs a flag is set, and a system reset can also be caused if it is enabled. The main use of
the Watchdog timer is as a system monitor. This is important in real-time control applications. In case
of power glitches or electro-magnetic interference, the processor may begin to execute errant code. If
this is left unchecked the entire system may crash. The watchdog time-out selection will result in
different time-out values depending on the clock speed. The Watchdog timer will de disabled on
reset. In general, software should restart the Watchdog timer to put it into a known state. The control
bits that support the Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit: 7
ENW
6
CLRW
5
WIDL
4
-
32
1
- PS2 PS1
0
PS0
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:
PS2 PS1 PS0
00 0
01 0
00 1
01 1
10 0
10 1
11 0
11 1
PRESCALER SELECT
2
4
8
16
32
64
128
256
Publication Release Date: January 1999
- 7 - Revision A2

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W78L51F-24

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