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W78LE54F-24 데이터시트 PDF




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기능 8-BIT MTP MICROCONTROLLER
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W78LE54F-24 데이터시트, 핀배열, 회로
Preliminary W78LE54
8-BIT MTP MICROCONTROLLER
GENERAL DESCRIPTION
The W78LE54 is an 8-bit microcontroller which can accommodate a wide supply voltage range with
low power consumption. The instruction set for the W78LE54 is fully compatible with the standard
8051. The W78LE54 contains an 16K bytes MTP ROM (Multiple-Time Programmable ROM); a 256
bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; three
16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported
by eight sources two-level interrupt capability. To facilitate programming and verification, the MTP-
ROM inside the W78LE54 allows the program memory to be programmed and read electronically.
Once the code is confirmed, the user can protect the code for security.
The W78LE54 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
Fully static design 8-bit CMOS microcontroller
Wide supply voltage of 2.4V to 5.5V
256 bytes of on-chip scratchpad RAM
16 KB electrically erasable/programmable MTP-ROM
64 KB program memory address space
64 KB data memory address space
Four 8-bit bi-directional ports
One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
Three 16-bit timer/counters
One full duplex serial port(UART)
Watchdog Timer
Eight sources, two-level interrupt capability
EMI reduction mode
Built-in power management
Code protection mechanism
Packages:
DIP 40: W78LE54-24
PLCC 44: W78LE54P-24
PQFP 44: W78LE54F-24
Publication Release Date: February 1999
- 1 - Revision A1




W78LE54F-24 pdf, 반도체, 판매, 대치품
Preliminary W78LE54
BLOCK DIAGRAM
P1.0
~
P1.7
Port
1
Port 1
Latch
INT2
INT3
Interrupt
Timer
2
Timer
0
Timer
1
UART
P3.0
~
P3.7
Port
3
Port 3
Latch
ACC
T1
B
T2
PSW
ALU
Stack
Pointer
Instruction
Decoder
&
Sequencer
SFR RAM
Address
256 bytes
RAM & SFR
Port 0
Latch
DPTR
Temp Reg.
PC
Incrementor
Addr. Reg.
P4.0
~
P4.3
Port
4
Port 4
Latch
Bus & Clock
Controller
ROM
Watchdog
Timer
Oscillator
Reset Block Power control
Port 2
Latch
XTAL1 XTAL2 ALE PSEN RST
Vcc Vss
P0.0
Port
0
~
P0.7
P2.0
Port
2
~
P2.7
FUNCTIONAL DESCRIPTION
The W78LE54 architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.
RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature
of the W78LE54: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
-4-

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W78LE54F-24 전자부품, 판매, 대치품
Preliminary W78LE54
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog
timer is as a system monitor. This is important in real-time control applications. In case of power
glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is
left unchecked the entire system may crash. The watchdog time-out selection will result in different
time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In
general, software should restart the Watchdog timer to put it into a known state. The control bits that
support the Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit: 7 6 5
ENW CLRW WIDL
4
-
3210
- PS2 PS1 PS0
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0 : Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:
PS2 PS1 PS0
00 0
01 0
00 1
01 1
10 0
10 1
11 0
11 1
PRESCALER SELECT
2
4
8
16
32
64
128
256
The time-out period is obtained using the following equation:
1 × 214 × PRESCALER ×1000 ×12 mS
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
Publication Release Date: February 1999
- 7 - Revision A1

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W78LE54F-24

8-BIT MTP MICROCONTROLLER

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