PDF W83194AR-73 Data sheet ( Hoja de datos )

Número de pieza	W83194AR-73
Descripción	150MHZ CLOCK FOR WHITNEY CHIPSET
Fabricantes	Winbond
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No Preview Available ! W83194AR-73 150MHZ CLOCK FOR WHITNEY CHIPSET 1.0 GENERAL DESCRIPTION The W83194AR-73 is a Clock Synthesizer for Intel Whitney chipset. W83194AR-73 provides all clocks required for high-speed RISC or CISC microprocessor and also provides 32 different frequencies of CPU, SDRAM, PCI, 3V66, IOAPIC clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194AR-73 provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.25% center and 0-0.5% down type spread spectrum to reduce EMI. The W83194AR-73 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 1.0 PRODUCT FEATURES • 2 CPU clocks • 9 SDRAM clocks for 2 DIMMs • 8 PCI synchronous clocks. • Optional single or mixed supply: (VDDR = VDDP=VDDS = VDD48 = VDD3 = 3.3V, VDDA=VDDC=2.5V) • Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns • Smooth frequency switch with selections from 66.8 to 150MHz • I2C 2-Wire serial interface and I2C read back • 0.25% center and 0-0.5% down type spread spectrum • Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) • 48 MHz for USB • 24 MHz for super I/O • Packaged in 48-pin SSOP Publication Release Date: May 1999 - 1 - Revision 0.40 1 page W83194AR-73 5.4 Register 3: PCI Clock Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 1 20 PCICLK7 (Active / Inactive) 6 1 19 PCICLK6 (Active / Inactive) 5 1 17 PCICLK5 (Active / Inactive) 4 1 16 PCICLK4 (Active / Inactive) 3 1 15 PCICLK3 (Active / Inactive) 2 1 13 PCICLK2 (Active / Inactive) 1 1 12 PCICLK1 (Active / Inactive) 0 1 11 PCICLK0 (Active / Inactive) 5.5 Register 4: Additional Register (1 = Active, 0 = Inactive) Bit @PowerUp Pin Description 7 X - SEL_3V66# 6 1 8 3V66_1(Active / Inactive) 5 1 7 3V66_0(Active / Inactive) 4 0 - Reserve 3 1 47 IOAPIC (Active / Inactive) 2 X - FS1# 1 1 44 CPUCLK1(Active / Inactive) 0 1 45 CPUCLK0(Active / Inactive) 5.6 Register 5: Reserve Register Bit @PowerUp Pin 7 0 - Reserve 6 0 - Reserve 5 0 - Reserve 4 0 - Reserve 3 0 - Reserve 2 0 - Reserve 1 0 - Reserve 0 0 - Reserve Description PRELIMINARY Publication Release Date: May 1999 - 5 - Revision 0.30 5 Page

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