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PDF W83194R-37 Data sheet ( Hoja de datos )
| Número de pieza | W83194R-37 | |
| Descripción | 100 MHZ AGP CLOCK FOR VIA CHIPSET | |
| Fabricantes | Winbond | |
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Preliminary W83194R-37/-58
100 MHZ AGP CLOCK FOR VIA CHIPSET
1.0 GENERAL DESCRIPTION
The W83194R-37/-58 is a Clock Synthesizer for VIA chipset. W83194R-37 provides all clocks
required for high-speed RISC or CISC microprocessor such as Intel PentiumPro, AMD or Cyrix. Eight
different frequencies of CPU, W83194R-58 provides all clocks required for high-speed RISC or CISC
microprocessor such as Intel PentiumII and also provides 16 different frequencies of CPU clocks by
software setting (additional register0 bit2). AGP and PCI clocks are externally selectable with smooth
transitions. The W83194R-37/-58 provides AGP clocks especially for clone chipset, and makes
SDRAM in synchronous frequency with CPU or AGP clocks.
The W83194R-37/-58 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and choose the 0.25%, 0.5% or 0.5%,1.5% center type spread spectrum to reduce
EMI.
The W83194R-37/-58 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1V /nS slew rate into 30 pF
loads. CPU CLOCK outputs typically provide better than 1V /nS slew rate into 20 pF loads as
maintaining 50 ±5% duty cycle. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide
better than 0.5V /nS slew rate.
2.0 FEATURES
• Supports Pentium™, Pentium™ Pro, Pentium™ II, AMD and Cyrix CPUs with I2C.
• 4 CPU clocks
• 12 SDRAM clocks for 3 DIMs
• Two AGP clocks
• 6 PCI synchronous clocks.
• Optional single or mixed supply:
(VDD = VDDq3 = VDDq2 = VDDq2b = 3.3V) or (VDD = VDDq3 = VDDq2 = 3.3V, VDDq2b = 2.5V)
• Skew form CPU to PCI clock -1 to 4 nS, center 2.6 nS, AGP to CPU sync. skew 0 nS (250 pS)
• SDRAM frequency synchronous to CPU or AGP clocks
• Smooth frequency switch with selections from 60 to 100 MHz CPU (-37) and 66 to 150 MHz (-58)
• I2C 2-Wire serial interface and I2C read back
• ±0.5% or ±1.5% (-37) and 0.25%, 0.5% (-58) center type spread spectrum to reduce EMI
• Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal)
• MODE pin for power Management
• 48 MHz for USB
• 24 MHz for super I/O
• Packaged in 48-pin SSOP
Publication Release Date: April 1999
- 1 - Revision A1
1 page  
Preliminary W83194R-37/-58
6.0 FREQUENCY SELECTION BY HARDWARE
6.1 W83194R-37 Frequency Selection Table
FS2 FS1 FS0 CPU (MHz) SDRAM (MHz) PCI (MHz) AGP (MHz) REF (MHz)
SD_SEL = 1 SD_SEL = 0
000
001
010
011
100
101
110
111
60
66.8
68.5
75
75
83.3
95
100
60 60
30
66.8 66.8 33.4
68.5 68.5 34.25
75 75 37.5
75 60
30
83.3 66.6 33.3
95 63.4 31.7
100 66.6 33.3
60 14.318
66.8 14.318
68.5 14.318
75 14.318
60 14.318
66.6 14.318
63.4 14.318
66.6 14.318
6.2 W83194R-58 Frequency Selection Table
FS2 FS1 FS0 CPU (MHz) SDRAM (MHz) PCI (MHz) AGP (MHz) REF (MHz)
SD_SEL = 1 SD_SEL = 0
000
001
010
011
100
101
110
111
112
66.8
124
75
133.3
83.3
95.25
100.2
112
66.8
124
75
133.3
83.3
95.25
100.2
74.7
66.8
82.5
75
88.7
66.6
63.5
66.8
37.3
33.4
41.3
37.5
44.3
33.3
31.75
33.4
74.7
66.8
82.5
75
88.7
66.6
63.5
66.8
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
7.0 CPU 3.3#_2.5 BUFFER SELECTION
CPU 3.3#_2.5 (Pin 2) Input Level
1
0
CPU Operate at
VDD = 2.5V
VDD = 3.3V
Publication Release Date: April 1999
- 5 - Revision A1
5 Page 
Preliminary W83194R-37/-58
9.0 SPECIFICATIONS
9.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs
must always be tied to an appropriate logic voltage level (Ground or VDD).
PARAMETER
SYMBOL
RATING
Voltage on any pin with respect to GND
VDD, VIN
- 0.5V to +7.0V
Storage Temperature
TSTG
- 65°C to +150°C
Ambient Temperature
TB - 55°C to +125°C
Operating Temperature
TA 0°C to +70°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
9.2 AC Characteristics
VDDq2 = VDD = VDDq3 = 3.3V ±5%, VDDq2b = 2.375V~2.9V , TA = 0 °C to +70 °C
PARAMETER
SYM. MIN. TYP. MAX. UNITS TEST CONDITIONS
Output Duty Cycle
45 50
55
% Measured at 1.5V
CPU/SDRAM to PCI Offset tOFF
1
4 nS 15 pF Load Measured at
1.5V
Skew (CPU-CPU), (PCI-
PCI), (SDRAM-SDRAM)
tSKEW
250 pS 15 pF Load Measured at
1.5V
CPU/SDRAM
Cycle to Cycle Jitter
tCCJ
±250 pS
CPU/SDRAM
Absolute Jitter
tJA
500 pS
Jitter Spectrum 20 dB
Bandwidth from Center
BWJ
500 KHz
Output Rise (0.4V−2.0V)
& Fall (2.0V−0.4V) Time
Overshoot/Undershoot
Beyond Power Rails
tTLH
tTHL
Vover
0.4
0.7
1.6 nS 15 pF Load on CPU and
PCI outputs
1.5 V 22 Ω at source of 8 inch
PCB run to 15 pF load
Ring Back Exclusion
VRBE 0.7
2.1 V Ring Back must not enter
this range.
- 11 -
Publication Release Date: April 1999
Revision A1
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet W83194R-37.PDF ] | |
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