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W83194R-58 데이터시트 PDF




Winbond에서 제조한 전자 부품 W83194R-58은 전자 산업 및 응용 분야에서
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부품번호 W83194R-58 기능
기능 100 MHZ AGP CLOCK FOR VIA CHIPSET
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W83194R-58 데이터시트, 핀배열, 회로
Preliminary W83194R-37/-58
100 MHZ AGP CLOCK FOR VIA CHIPSET
1.0 GENERAL DESCRIPTION
The W83194R-37/-58 is a Clock Synthesizer for VIA chipset. W83194R-37 provides all clocks
required for high-speed RISC or CISC microprocessor such as Intel PentiumPro, AMD or Cyrix. Eight
different frequencies of CPU, W83194R-58 provides all clocks required for high-speed RISC or CISC
microprocessor such as Intel PentiumII and also provides 16 different frequencies of CPU clocks by
software setting (additional register0 bit2). AGP and PCI clocks are externally selectable with smooth
transitions. The W83194R-37/-58 provides AGP clocks especially for clone chipset, and makes
SDRAM in synchronous frequency with CPU or AGP clocks.
The W83194R-37/-58 provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and choose the 0.25%, 0.5% or 0.5%,1.5% center type spread spectrum to reduce
EMI.
The W83194R-37/-58 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1V /nS slew rate into 30 pF
loads. CPU CLOCK outputs typically provide better than 1V /nS slew rate into 20 pF loads as
maintaining 50 ±5% duty cycle. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide
better than 0.5V /nS slew rate.
2.0 FEATURES
Supports Pentium, PentiumPro, PentiumII, AMD and Cyrix CPUs with I2C.
4 CPU clocks
12 SDRAM clocks for 3 DIMs
Two AGP clocks
6 PCI synchronous clocks.
Optional single or mixed supply:
(VDD = VDDq3 = VDDq2 = VDDq2b = 3.3V) or (VDD = VDDq3 = VDDq2 = 3.3V, VDDq2b = 2.5V)
Skew form CPU to PCI clock -1 to 4 nS, center 2.6 nS, AGP to CPU sync. skew 0 nS (250 pS)
SDRAM frequency synchronous to CPU or AGP clocks
Smooth frequency switch with selections from 60 to 100 MHz CPU (-37) and 66 to 150 MHz (-58)
I2C 2-Wire serial interface and I2C read back
±0.5% or ±1.5% (-37) and 0.25%, 0.5% (-58) center type spread spectrum to reduce EMI
Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal)
MODE pin for power Management
48 MHz for USB
24 MHz for super I/O
Packaged in 48-pin SSOP
Publication Release Date: April 1999
- 1 - Revision A1




W83194R-58 pdf, 반도체, 판매, 대치품
Preliminary W83194R-37/-58
5.3 I2C Control Interface
SYMBOL
SDATA
SDCLK
PIN
23
24
I/O FUNCTION
I/O Serial data of I2C 2-wire control interface
IN Serial clock of I2C 2-wire control interface
5.4 Fixed Frequency Outputs
SYMBOL
REF0/ CPU3.3#_2.5
PIN
2
REF1/*SD_SEL#
46
24MHz/ *MODE
25
48MHz/ *FS0
26
I/O FUNCTION
I/O Internal 250 Kpull-up.
Latched input for CPU3.3#_2.5 at initial power up.
Reference clock during normal operation.
Latched high - VDDq2b = 2.5V
Latched low - VDDq2b = 3.3V
I/O Internal 250 Kpull-up.
Latched input at Power On selects either CPU(SDSEL = 1)
or AGP(SD_SEL = 0) frequencies for SDRAM clock
outputs.
I/O Internal 250 Kpull-up.
Latched input for MODE at initial power up. 24 MHz output
for super I/O during normal operation.
I/O Internal 250 Kpull-up.
Latched input for FS0 at initial power up for H/W selecting
the output frequency of CPU, SDRAM and PCI clocks. 48
MHz output for USB during normal operation.
5.5 Power Pins
SYMBOL
VDD
VDDq2
VDDq2b
VDDq3
Vss
PIN FUNCTION
1 Power supply for Ref [0:1] crystal and core logic.
42 Power supply for AGP1 and REF1 output, either 2.5V or
3.3V.
48 Power supply for CPUCLK[0:3], either 2.5V or 3.3V.
6, 14, 19, 30, 36 Power supply for SDRAM, PCICLK and 48/24 MHz outputs.
3, 9, 16, 22, 27, Circuit Ground.
33, 39, 45
-4-

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W83194R-58 전자부품, 판매, 대치품
Preliminary W83194R-37/-58
8.3 Serial Control Registers
The Pin column lists the affected pin number and the @PowerUp column gives the state at true
power up. Registers are set to the values shown only on true power up. "Command Code" byte and
"Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data
(bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After
that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
8.3.1 Register 0: CPU Frequency Select Register
BIT @POWERUP PIN
DESCRIPTION
7 0 - 0 = ±1.5% Spread Spectrum Modulation (W83194R-37)
1 = ±0.5% Spread Spectrum Modulation
0 = ±0.25% Center Type Spread Spectrum Modulation (W83194R-58)
1 = ±0.5% Center Type Spread Spectrum Modulation
6 0 - SSEL2 (Frequency table selection by software via I2C)
5 0 - SSEL1 (Frequency table selection by software via I2C)
4 0 - SSEL0 (Frequency table selection by software via I2C)
3 0 - 0 = Selection by hardware
1 = Selection by software I2C - Bit 6:4
2 0 - SSEL3 (Frequency table selection by software via I2C for
W83194R-58)
2 0 - 0 = Spread spectrum center type (W83194R-37)
1 = Spread spectrum down type (W83194R-37)
1 0 - 0 = Normal
1 = Spread Spectrum enabled
0 0 - 0 = Running
1 = Tristate all outputs
W83194R-37 Frequency table selection by software via I2C
SSEL2 SSEL1 SSEL0
CPU(MHz)
SDRAM
SD_SEL=1
(MHz)
SD_SEL=0
00 0
60
60 60
0 0 1 66.8 66.8 66.8
0 1 0 68.5 68.5 68.5
01 1
75
75 75
10 0
75
75 60
1 0 1 83.3 83.3 66.6
11 0
95
95 63.4
1 1 1 100 100 66.6
PCI
(MHz)
30
33.4
34.25
37.5
30
33.3
31.7
33.3
AGP
(MHz)
60
66.8
68.5
75
60
66.6
63.4
66.6
REF (MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
Publication Release Date: April 1999
- 7 - Revision A1

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