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PDF PCF88331 Data sheet ( Hoja de datos )
| Número de pieza | PCF88331 | |
| Descripción | STN RGB - 132 X 132 X 3 driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
PCF8833
STN RGB - 132 × 132 × 3 driver
Objective specification
2003 Feb 14
1 page  
Philips Semiconductors
STN RGB - 132 × 132 × 3 driver
Objective specification
PCF8833
5 PINNING
SYMBOL
R95 to R64
C0 to C395
R0 to R31
R63 to R32
RES
TE
VSS1
VSS2
CS/SCE
VDD1
VDD3
VDD2
D7
D3
D6
D2
D5
D1
D4
D0/SDIN
SDOUT
D/C/SCLK
WR
RD
PS0
PS1
PS2
PAD
2 to 33
34 to 429
430 to 461
464 to 495
496
497
498 to 507
508 to 517
518
519 to 524
525 to 529
530 to 539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
TYPE
DESCRIPTION
O LCD row driver outputs
O LCD column driver outputs
O LCD row driver outputs
O LCD row driver outputs
I external reset; this signal will reset the device and must be applied to properly
initialize the chip (active LOW)
O/I tearing line (in Normal mode it is always an output)
PS system ground
PS system ground
I chip select parallel interface or serial chip enable (active LOW)
PS logic supply voltage
PS VDD2 and VDD3 are the supply voltage pins for the internal voltage generator
PS including the temperature compensation circuits; VDD2 and VDD3 can be
connected together but in this case care must be taken to respect the supply
voltage range (see Chapter 13); VDD1 is used as the supply for the rest of the
chip. VDD1 can be connected together with VDD2 and VDD3 but in this case care
must also be taken to respect the supply voltage range; see Chapter 13. VDD2
and VDD3 must not be applied before VDD1.
If the internal voltage generator is not used, pins VDD2 and VDD3 must be
connected to VDD1.
I/O 8-bit parallel data; in Serial mode tie to VSS1 or VDD1
I/O 8-bit parallel data; in Serial mode tie to VSS1 or VDD1
I/O 8-bit parallel data; in Serial mode tie to VSS1 or VDD1
I/O 8-bit parallel data; in Serial mode tie to VSS1 or VDD1
I/O 8-bit parallel data; in Serial mode tie to VSS1 or VDD1
I/O 8-bit parallel data; in Serial mode tie to VSS1 or VDD1
I/O 8-bit parallel data; in Serial mode tie to VSS1 or VDD1
I/O 8-bit parallel data or serial data input
O serial data output; in Parallel mode tie to VDD1, VSS1 or D0
I data/command indicator parallel interface or serial clock
I write clock parallel interface; in Serial mode tie to VDD1 (active LOW)
I read clock parallel interface; in Serial mode tie to VDD1 (active LOW)
I set serial or parallel interface mode PS1 and PS2 must tied to either VSS1 or
VDD1
I set serial or parallel interface mode PS1 and PS2 must tied to either VSS1 or
VDD1
I set serial or parallel interface mode PS1 and PS2 must tied to either VSS1 or
VDD1
2003 Feb 14
5
5 Page 
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D/C 7
01
01
01
01
1X
01
1 OS7
65432
10110
10111
11011
11100
X ORA2 ORA1 ORA0 X
11100
OS6 OS5 OS4 OS3 OS2
1
1
0
1
0
OPE
0
OS1
0 DEFAULT OTP
DESCRIPTION
1
DBH
x read ID2 (RDID2)
0
SFD
DCH
EFH
x read ID3 (RDID3)
x select factory defaults(3)
0 F0H − enter Calibration mode
CALMM 00H
− set calibration control settings
1 F1H − shift data in OTP shift registers
(OTPSHTIN)
OS0
XX − multiple data byte; any number
of bytes allowed
SECTION
6.2.46
6.2.46
6.2.47
15.5
15.5
15.5
15.5
Notes
1. X = don’t care.
2. This function can be set by OTP.
3. If the OTP bit Enable Factory Defaults (EFD) has been programmed to logic 1 (default value is logic 0), then the Set Factory Defaults (SFD)
instruction is ignored and the device will always use the OTP default data.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PCF88331.PDF ] | |
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