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W981616BH 데이터시트 PDF




Winbond에서 제조한 전자 부품 W981616BH은 전자 산업 및 응용 분야에서
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부품번호 W981616BH 기능
기능 512K 2 BANKS 16 BITS SDRAM
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W981616BH 데이터시트, 핀배열, 회로
W981616BH
512K × 2 BANKS × 16 BITS SDRAM
GENERAL DESCRIPTION
W981616BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words × 2 banks × 16 bits. Using pipelined architecture and 0.175 µm process technology,
W981616BH delivers a data bandwidth of up to 332M bytes per second (-5). For different applications
the W981616BH is sorted into the following speed grades: -5, -6, and –7(L).
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W981616BH is ideal for main memory in
high performance applications.
FEATURES
3.3V ±0.3V power supply
Up to 166 MHz clock frequency
524,288 words x 2 banks x 16 bits organization
Auto Refresh and Self Refresh
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Burst read, Single Write Mode
Byte data controlled by UDQM and LDQM
Auto-precharge and controlled precharge
4K refresh cycles/64 mS
Interface: LVTTL
Packaged in 50-pin, 400 mil TSOP II
PIN CONFIGURATION
VCC
DQ0
DQ1
VSS Q
DQ2
DQ3
VCCQ
DQ4
DQ5
VSS Q
DQ6
DQ7
VCCQ
LDQM
WE
CAS
RAS
CS
BA
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 VSS
49 DQ15
48 DQ14
47 VSS Q
46 DQ13
45 DQ12
44 VCCQ
43 DQ11
42 DQ10
41 VSS Q
40 DQ9
39 DQ8
38 VCCQ
37 NC
36 UDQM
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
Publication Release Date: February 2000
- 1 - Revision A2




W981616BH pdf, 반도체, 판매, 대치품
W981616BH
FUNCTIONAL DESCRIPTION
Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs during power up, all VCC and VCCQ pins must be ramp up simultaneously to the
specified voltage when the input signals are held in the "NOP" state. The power up voltage must not
exceed VCC +0.3V on any of the input pins or VCC supplies. After power up, an initial pause of 200 µS
is required followed by a precharge of all banks using the precharge command. To prevent data
contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high
during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles
(CBR) are also required before or after programming the Mode Register to ensure proper subsequent
operation.
Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during
this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new
command may be issued following the mode register set command once a delay equal to tRSC has
elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and
vice versa) is the Bank-to-Bank delay time (tRRD). The maximum time that each bank can be held
active is specified as tRAS(max.).
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by
setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin
voltage level defines whether the access cycle is a read operation ( WE high), or a write operation
( WE low). The address inputs determine the starting column address. Reading or writing to a
different row within an activated bank requires the bank be precharged and a new Bank Activate
command be issued. When more than one bank is activated, interleaved bank Read or Write
operations are possible. By using the programmed burst length and alternating the access and
precharge operations between multiple banks, seamless data access operation among many different
pages can be realized. Read or Write Commands can also be issued to the same bank or between
active banks on every clock cycle.
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W981616BH 전자부품, 판매, 대치품
W981616BH
Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is
entered. During auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS latency.
A Read or Write Command with auto-precharge can not be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during
a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot
be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-Precharge command is
illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write
with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation
one clock delay from the last burst write cycle. This delay is referred to as Write tDPL. The bank
undergoing auto-precharge can not be reactivated until tDPL and tRP are satisfied. This is referred to as
tDAL, Data-in to Active delay (tDAL = tDPL + tRP). When using the Auto-precharge Command, the interval
between the Bank Activate Command and the beginning of the internal precharge operation must
satisfy tRAS(min).
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising
edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, and BA, are used to define which bank(s) is to be
precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge
time (tRP).
Self Refresh Command
The Self-Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high
at the rising edge of the clock. All banks must be idle prior to issuing the Self-Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self-Refresh Operation to save power. The device
will exit Self-Refresh operation after CKE is returned high. Any subsequent commands can be issued
after tRC from the end of Self Refresh command.
If, during normal operation, Auto-Refresh cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 Auto-Refresh cycles should be completed just prior to entering and just
after exiting the Self-Refresh mode.
Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations;
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
Publication Release Date: February 2000
- 7 - Revision A2

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W981616BH

512K 2 BANKS 16 BITS SDRAM

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