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W986432DH 데이터시트 PDF




Winbond에서 제조한 전자 부품 W986432DH은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 W986432DH 기능
기능 512K 4 BANKS 32 BITS SDRAM
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W986432DH 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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W986432DH 데이터시트, 핀배열, 회로
PRELIMINARY W986432DH
512K × 4 BANKS × 32 BITS SDRAM
GENERAL DESCRIPTION
W986432DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words × 4 banks × 32 bits. Using pipelined architecture and 0.175 µm process technology,
W986432DH delivers a data bandwidth of up to 800M bytes per second (5). For different application,
W986432DH is sorted into four speed grades: -5, -55, -6, -7,-8.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W986432DH is ideal for main memory in
high performance applications.
FEATURES
3.3V ±0.3V power supply
524288 words × 4 banks × 32 bits organization
Auto Refresh and Self Refresh
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Sequential and Interleave burst
Burst read, single write operation
Byte data controlled by DQM
Power-down Mode
Auto-precharge and controlled precharge
4K refresh cycles/64 mS
Interface: LVTTL
Packaged in 86-pin TSOP II, 400 mil - 0.50
Publication Release Date: May 2000
- 1 - Revision A0




W986432DH pdf, 반도체, 판매, 대치품
BLOCK DIAGRAM
W986432DH
CLK
CKE
CS
RAS
CAS
WE
CLOCK
BUFFER
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10
A0 MODE
REGISTER
ADDRESS
A9 BUFFER
BS0
BS1
REFRESH
COUNTER
COLUMN
COUNTER
COLUMN DECODER
CELL ARRAY
BANK #0
SENSE AMPLIFIER
DATA CONTROL
CIRCUIT
COLUMN DECODER
CELL ARRAY
BANK #2
SENSE AMPLIFIER
COLUMN DECODER
CELL ARRAY
BANK #1
SENSE AMPLIFIER
DQ
BUFFER
DQ0
DQ31
DQM0~3
COLUMN DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
NOTE:
The cell array configuration is 2048 * 256 * 32
-4-

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W986432DH 전자부품, 판매, 대치품
W986432DH
AC CHARACTERISTICS
(VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0 to 70 °C) (Notes: 5, 6.)
PARAMETER
Symbol
-5
-55
-6 UNIT NOTE
MIN MAX MIN MAX MIN MAX
Ref/Active to Ref/Active Command Period tRC
54
55
60
ns
Active to precharge Command Period
tRAS
40 100000 40 100000 42 100000
Active to Read/Write Command Delay TimetRCD
14
15
18
Read/Write(a) to Read/Write(b)Command tCCD
1
1
1 Cycle
Period
Precharge to Active(b) Command Period tRP
14
15
18
ns
Active(a) to Active(b) Command Period tRRD
10
10.8
12
Write Recovery Time
CL* = 2 tWR
7
7.5 7.5
CL* = 3
5 5.4 6
CLK Cycle Time
CL* = 2 tCK
7 1000 7.5 1000 7.5 1000
CL* = 3
5 1000 5.4 1000 6 1000
CLK High Level
tCH 2 2 2
CLK Low Level
tCL 2 2 2
Access Time from CLK
CL* = 2 tAC
4.5 5.5 5.5
CL* = 3
4.5 5
5
Output Data Hold Time
tOH 2.75 2.75 2.75
Output Data High Impedance Time
tHZ 2.75 5 2.75 5.4 2.75 6
Output Data Low Impedance Time tLZ 0 0 0
Power Down Mode Entry Time
tSB 0 5 0 5.4 0 6
Transition Time of CLK (Rise and Fall) tT
0.5 10 0.5 10 0.5 10
Data-in-Set-up Time
tDS 1
1.5 1.5
Data-in Hold Time
tDH 0.5 0.5 0.5
Address Set-up Time
tAS 1.3 1.5 1.5
Address Hold Time
tAH 0.8 1 0.5
CKE Set-up Time
tCKS
1.3
1.5
1.5
CKE Hold Time
tCKH
0.8
1
0.5
Command Set-up Time
tCMS
1
1.5 1.5
Command Hold Time
tCMH 0.5 0.5 0.5
Refresh Time
tREF
64 64
64 ms
Mode Register Set Cycle Time
tRSC
10
10.8
12
ns
Publication Release Date: May 2000
- 7 - Revision A0

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W986432DH

512K 4 BANKS 32 BITS SDRAM

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