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부품번호 | WARP11 기능 |
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기능 | WEIGHT ASSOCIATIVE RULE PROCESSOR | ||
제조업체 | STMicroelectronics | ||
로고 | ![]() |
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![]() W.A.R.P. 1.1
WEIGHT ASSOCIATIVE RULE PROCESSOR
ADVANCED DATA
High Speed Rules Processing
Antecedent Membership Functions with any
Shape
Up to 256 Rules (4 Antecedents,1
Consequent)
Up to 16 Input Configurable Variables
Up to 16 Membership Functions for an Input
Variable
Up to 16 Output Variables
Up to 128 Membership Functions for all
Consequents
MAX-DOT Inference Method
Defuzzification on chip
Software Tools and Emulators Availability
100-pin CPGA100 Ceramic Package
84-lead Plastic Leaded Chip Carrier package
GENERAL DESCRIPTION
W.A.R.P. is a VLSI Fuzzy Logic controller whose
architecture arises from the need of realizing an
integrated structure with high inferencing perform-
ances and flexibility. To get those results a modular
architecture based on a set of parallel memory
blocks has been implemented.
In order to obtainhigh performances W.A.R.P. uses
different data representations during the various
phases of the computational cycle, so that it is
always operating on the optimal data repre-
sentation. A vectorial characterization has been
adopted for the Antecedent Membership Func-
tions. W.A.R.P. exploits a SGS-THOMSON pat-
ented strategy to store the AntecedentMembership
CPGA 100
PLCC84
Figure 1. Logic Diagram
MCLK VS S VDD
FIN
S YNC
8
10
O0-O9
4
I0-I7 W.A.R.P.
O CNT0- O CNT3
3 1.1
STB
EPA 0- E PA2
NP
10
A0-A9
EP
CHM OFL PRS T
Table 1. W.A.R.P. Configuration Settings
Number of Inputs
Standard Rule Format
Rules Number
Antecedent’s MFs Number
Consequent’s MFs Number
Input Data Resolution
Output Data Resolution
Configurable [1..8]
4 Antecedents, 1 Consequent [or subsets]
Max 256 Rules in the 4 Antecedent, 1 Consequent format
Configurable [up to 16 for an input variable]
Max 256 for all outputs variables
8 bit
8 bit
May 1996
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without no tice.
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![]() ![]() W.A.R.P.1.1
Table 4. Pin Description
Name
VDD
VSS
A0-A9
I0-I7
PRST
FIN
OFL
CHM
TE
MTE
MCLK
EPA0-EPA2*
O0-O9
OCNT0-OCNT3
STB
EP
NP
OTST
OMTS
SYNC
Pins Type
-
-
I/O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
* Pins not used in W.A.R.P. 1.0
Functions in dedicated memories in order to reduce
the computational time. Therefore a great amount
of W.A.R.P. processing is based on a look-up table
approach rather than on on-line calculation.
Those Membership Functions (MFs), each one
portrayed by a configurable resolution of 26 or 27
elements, are stored in four internal RAMs (1Kbyte
each). The consequent MFs, due to the different
modelling, are loaded in a single RAM by storing
for each MF its area and its barycentre. This is due
to the adoption of the Center of Gravity defuzzifica-
tion method.
The downloading phase allows the setting of the
device, in terms of I/O number, universes of dis-
course and MF shapes. During this phase W.A.R.P.
prepares its internal memories for the on-line
elaboration phase and loads the microcode in its
program memory. This microcode, which drives the
on-line phase, is generated by the Compiler (see
W.A.R.P.-SDT User Manual) according to the
adopted configuration. The possible configurations
are shown in table 1.
During the on-line phase (up to 40MHz working
frequency), W.A.R.P. processes the input data and
produces its outputs according to the configuration
loaded in the downloading phase.
W.A.R.P. is conceived to work together with tradi-
Function
Power Supply
Ground
Memory Address Bus
Data Input Bus
Preset
First Input Signal
Off-Line/On-Line Switch
Charge Mode Switch
Testing (it must be connected to VSS)
Testing (it must be connected to VSS)
Clock (up to 40 MHz)
EPROM Address Bus
Defuzzified Output
Output Counter
Strobe (Output Ready Signal)
End Process
New Process
Testing (it must be connected to VSS)
Testing (it must be connected to VSS)
External Synchronization
tional microcontrollers which shall perform normal
control tasks while W.A.R.P. will be indipendently
responsible for all the fuzzy related computing.
W.A.R.P. is manufactured using the high perform-
ance, reliable HCMOS4T (O.7µm) SGS-THOM-
SON Microelectronics process.
PIN DESCRIPTION
VDD, VSS: Power is supplied to W.A.R.P. using
these pins. VDD is the power connection and VSS is
the ground connection; multi-connections are nec-
essary.
A0-A9: When the CHM pin is low they accept as
input the addresses for the internal memory bus. In
the off-line mode they are used to address W.A.R.P.
memories where the microprogram and data of
antecedent and consequentmembership functions
must be loaded.
Each A0-A9 word is composed by assembling the
data contained in the memory support related to .cs
and .add files (see W.A.R.P.-SDT User Manual). In
particular, couples of data respectively coming from
.cs and .add files are joined to form a single A0-A9
word in the following way:
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4페이지 ![]() ![]() W.A.R.P.1.1
provided by W.A.R.P. by means of A0-A9 and
EPA0-EPA2 output pins.
Data must be loaded 8 bit a time in the data bus
and can be read from an external non volatile
memory or loaded by an host processor.
ON-LINE MODE
In On-line mode W.A.R.P. is enabled to elaborate
input values and calculate outputs according to the
fuzzy rules stored into the microprogram. W.A.R.P.
reads the input values one a time in the input data
bus when all the inputs are given, a NP signal is
pulled high to indicate that the computation is start-
ing. The computational phase is divided in two main
parts. During the first one the input values are read
and the corresponding ALPHA values (activation
levels) are extracted from the internal memories. In
the second part the computation of the fuzzy rules
and the defuzzification are implemented.
The block diagram shown in figure 3 describes the
structure of W.A.R.P..
Antecedent Memory. It is formed by 4 benchs
each one containing one to four fuzzy sets bonded
to the input variables.
Consequent Memory. It is formed by one bench
where the fuzzy sets bondedto the output variables
are stored .
Program Memory. It is formed by a single bench.
Each line contains an operating code to execute
the computation of a rule. This code selects the
antecedentweights (ALPHA) involved in a rule, and
connects them by the programmed connective op-
erators (AND,OR).
Input Router. This internal block performs the
input data routing. Data are read one byte a time
from the input data bus, stored in 4 different buffers
and, thanks to a pipeline process, sent together to
4 indipendent modules to be processed in parallel
according to the chosen set-up configuration. Input
data resolution is decided by the user (MAX 128
points) according to the available configurations,
as shown in table 5.
The cycle starts when a positive pulse is applied at
FIN for a time no lower than an entire clock period
and continues until a new FIN (after NP low) or a
PRST signal is given.
Fuzzifier. This block generates the addresses of
the antecedentmemories where the ALPHA values
for each sampled input value are stored. It reads
the first four input values and calculates the corre-
sponding antecedent memories addresses. After-
wards it reads other four inputs values and
simultaneously sends, thanks to a pipeline proc-
ess, the previous four ALPHA values into internal
registers. These ALPHAvalues are then sent to the
Inference Unit. W.A.R.P. stores all ALPHA values
comprising a term set, which is formed by the MFs
connected to the IF-part of a rule, in successive
memory locations of the same memory word (see
figure 4). The vectors characterizing the MFs of a
term set are stored so that the ALPHAs of different
MFs corresponding to the same universe of dis-
course point (for the same input) are stored se-
quentially. So W.A.R.P. retrieves all the alpha
values of a term set using the crisp input value to
calculate the memory word address in the used
fuzzy memory device.The Fuzzifier Unit is driven
Figure 5. Antecedent Memory Organization
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WARP11 | WEIGHT ASSOCIATIVE RULE PROCESSOR | ![]() STMicroelectronics |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |