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WEDPNF8M721V-1212BM 데이터시트 PDF




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기능 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
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WEDPNF8M721V-1212BM 데이터시트, 핀배열, 회로
White Electronic Designs WEDPNF8M721V-XBX
8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module
Multi-Chip Package ADVANCED*
FEATURES
n Sector Architecture
n Package:
• 275 Plastic Ball Grid Array (PBGA), 32mm x 25mm
n Commercial, Industrial and Military Temperature Ranges
n Weight:
• WEDPNF8M721V-XBX - 2.5 grams typical
• One 16KByte, two 8KBytes, one 32KByte, and fif
teen 64KBytes in byte mode
• One 8K word, two 4K words, one 16K word, and
fifteen 32K word sectors in word mode.
• Any combination of sectors can be concurrently
erased. Also supports full chip erase
SDRAM PERFORMANCE FEATURES
n Organized as 8M x 72
n High Frequency = 100, 125MHz
n Single 3.3V ±0.3V power supply
n Fully Synchronous; all signals registered on positive
edge of system clock cycle
n Boot Code Sector Architecture (Bottom)
n Embedded Erase and Program Algorithms
n Erase Suspend/Resume
• Supports reading data from or programing data to a
sector not being erased
BENEFITS
n Internal pipelined operation; column address can be
changed every clock cycle
n Internal banks for hiding row access/precharge
n Programmable Burst length 1,2,4,8 or full page
n 4096 refresh cycles
FLASH PERFORMANCE FEATURES
n User Configurable as 1Mx8 or 512Kx16
n Access Times of 100, 120, 150ns
n 3.3 Volt for Read and Write Operations
n 1,000,000 Erase/Program Cycles
n 42% SPACE SAVINGS
n Reduced part count
n Reduced I/O count
• 14% I/O Reduction
n Suitable for hi-reliability applications
n SDRAM Upgradeable to 16M x 72 density (contact
factory for information)
n Flash upgradeable to 2M x 8 (or 1M x 16 or 512K x 32)
density
* This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.
September 2002 Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com




WEDPNF8M721V-1212BM pdf, 반도체, 판매, 대치품
White Electronic Designs WEDPNF8M721V-XBX
Signal Name
VCC
GND
FD0 - 15
RYBY1
RST
BYTE1
FD16* - 31*
RYBY2*
BYTE2*
FA1-19
FCS1
FCS2*
FWE
FOE
A0 - A11
BA0 - 1
CS0
WE0
CLK0
CKE0
RAS0
CAS0
DQML0
DQMH0
CS1
WE1
CLK1
CKE1
RAS1
CAS1
DQML1
DQMH1
CS2
WE2
CLK2
CKE2
RAS2
CAS2
DQML2
DQMH2
CS3
WE3
CLK3
CKE3
RAS3
PACKAGE PINOUT LISTING
Pin Number
D15, E15, F8, F10, F15, G4, H4, J14, J15, J16, J17, K2, K3, K4, K5, L14, L15, L16, M5, M14, M15, N4, N5, N7, N8, N14, P4, P5, P6,
P7, P11, P12, P13, P14, R4, T15, U15, V15
D4, D16, E4, F4, F7, F9, F11, F12, F13, G14, G15, H15, J2, J3, J4, J5, K14, K15, K16, K17, L4, L5, M4, N6, N9, N10, N11, N12, N13,
N15, P8, P9, P10, P15, R15, T4, U4, V4
E8, C8, E9, C9, C10, D11, C11, D12, D8, B8, D9, D10, E10, E11, E12, E13
H5
A7
D13
C12, C15, A15, B9, B11, B13, A10, A12, C13, B15, B14, B10, B12, A9, A11, A14
A8
A13
F14, F5, E7, E6, E5, D6, D5, C6, C5, C4, B6, B5, B4, A6, A5, A4, C14, D7, C7
H14
E14
B7
D14
V12, U13, V13, V14, T14, R13, T13, R12, T12, R11, U12, T11
U11, V11
H3
E3
C3
B3
G3
F3
H2
D3
H18
J18
B18
A18
G18
F18
E18
C18
T18
R18
L18
K18
U18
V18
V17
M18
U3
V3
M3
L3
T3
*FD16-31, RY/BY2, BYTE2 are NC in this part, and used for flash upgrade to WEDPNF8M722V-XBX
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
4

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WEDPNF8M721V-1212BM 전자부품, 판매, 대치품
White Electronic Designs WEDPNF8M721V-XBX
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1,2,3,4)
(VCC = +3.3V ±0.3V; TA = -55°C TO +125°C)
Parameter/Condition
SDRAM Operating Current: Active Mode;
Burst = 2; Read or Write; tRC = tRC (min); CAS latency = 3 (5, 6, 7); FCS = High
SDRAM Standby Current: Active Mode; CKE = HIGH; CS = HIGH; FCS = High;
All banks active after tRCD met; No accesses in progress (5, 7, 8)
SDRAM Operating Current: Burst Mode; Continuous burst; FCS = High
Read or Write; All banks active; CAS latency = 3 (5, 6, 7)
SDRAM Self Refresh Current; FCS = High (14)
Symbol
ICC1
ICC3
ICC4
ICC7
Max
750
250
750
10
Units
mA
mA
mA
mA
Flash VCC Active Current for Read : FCS = VIL, FOE = VIH, f = 5MHz (9), CS = High, CKE = Low
IFCC1
32
mA
Flash VCC Active Current for Program or Erase: FCS = VIL, FOE = VIH, CS = High, CKE = Low
IFCC2
50
mA
Standby Current: VCC = 3.6 Max, FCS = VIH, CS = High, CKE = Low
ICC3 20 mA
NOTES:
1. All voltages referenced to VSS.
2. An initial pause of 100ms is required after power-up, followed by two
AUTO REFRESH commands, before proper device operation is ensured. (VCC
must be powered up simultaneously.) The two AUTO REFRESH command
wake-ups should be repeated any time the tREF refresh requirement is
exceeded.
3. AC timing and ICC tests have VIL = 0V and VIH = 3V, with timing referenced
to 1.5V crossover point.
4. ICC specifications are tested after the device is properly initialized.
5. ICC is dependent on output loading and cycle rates. Specified values are
obtained with minimum cycle time and the outputs open.
6. The ICC current will decrease as the CAS latency is reduced. This is due to
the fact that the maximum cycle rate is slower as the CAS latency is reduced.
7. Address transitions average one transition every two clocks.
8. Other input signals are allowed to transition no more than once every two
clocks and are otherwise at valid VIH or VIL levels.
9. The ICC current listed includes both the DC operating current and the
frequency dependent component (at 5 MHz). The frequency component
typically is less than 8 mA/MHz, with OE at VIH.
10. ICC active while Embedded Algorithm (program or erase) is in progress.
11. Maximum ICC specifications are tested with VCC = VCC Max.
12. Automatic sleep mode enables the low power mode when addressed
remain stable for tacc + 30 ns.
13. SDRAM inactive and in Power Down mode, all banks idle.
14. Self refresh available in commercial and industrial temperatures only.
SDRAM DESCRIPTION
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dy-
namic random-access ,memory using 5 chips containing
134, 217, 728 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of the
chip’s 33,554,432-bit banks is organized as 4,096 rows by
512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE com-
mand, which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0, BA1 select the bank; A0-11 select the row).
The address bits registered coincident with the READ or
WRITE command are used to select the starting column lo-
cation for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a
burst terminate option. An AUTO PRECHARGE function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence.
The 64MB SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compat-
ible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock
cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seam-
less, high-speed, random-access operation.
The 64MB SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, in-
cluding the ability to synchronously burst data at a high data
rate with automatic column-address generation, the ability
to interleave between internal banks in order to hide
precharge time and the capability to randomly change col-
umn addresses on each clock cycle during a burst access.
SDRAM FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
7 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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