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PDF WM2614 Data sheet ( Hoja de datos )

Número de pieza WM2614
Descripción Quad 12-bit Serial Input Voltage Output DAC
Fabricantes Wolfson Microelectronics plc 
Logotipo Wolfson Microelectronics plc Logotipo



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No Preview Available ! WM2614 Hoja de datos, Descripción, Manual

WM2614
Quad 12-bit Serial Input Voltage Output DAC
Production Data, June 1999, Rev 1.0
FEATURES
Quad 12-bit DAC voltage output DAC
Dual 2.7V to 5.5V supply (separate digital and analogue
supplies)
DNL ±0.4 LSB, INL ±1.5 LSB
Low power consumption:
- 5.5mW, slow mode 5V supply
- 3.3mW, slow mode 3V supply
TMS320, (Q)SPI, and Microwirecompatible serial
interface
Programmable settling time of 4µs or 12µs typical
APPLICATIONS
Battery powered test instruments
Digital offset and gain adjustment
Battery operated/remote industrial controls
Machine and motion control devices
Wireless telephone and communication systems
Speech synthesis
Arbitrary waveform generation
ORDERING INFORMATION
DEVICE
TEMP. RANGE
PACKAGE
WM2614CDT
0° to 70°C
16-pin TSSOP
WM2614IDT
-40° to 85 °C
16-pin TSSOP
DESCRIPTION
The WM2614 is a quadruple 12-bit voltage output, resistor string,
digital-to-analogue converter. Each DAC can be individually
powered down under software control. A hardware controlled mode
is provided that powers down all DACs. Power down reduces
current consumption to 10nA.
The device has been designed to interface efficiently to industry
standard microprocessors and DSPs, including the TMS320
family. The WM2614 is programmed with a 16-bit serial word
comprising of a DAC address, individual DAC control bits and a
12-bit value.
The WM2614 has provision for two supplies: one supply for the
serial interface (DVDD, DGND) and one for the DACs, reference
buffers and output buffers (AVDD, AGND). This enables a typical
application where the device can be controlled via a
microprocessor operating on a 3V supply, with the DACs operating
on a 5V supply. Alternatively, the supplies can be tied together in a
single supply application.
Excellent performance is delivered with a typical DNL of 0.4 LSBs.
The settling time of the DAC is programmable to allow the designer
to optimize speed versus power dissipation. The output stage is
buffered by a x2 gain near rail-to-rail amplifier, which features a
Class AB output stage. DACs A and B can have a different
reference voltage to DACs C and D.
The device is available in a 16-pin TSSOP package.
Commercial temperature (0° to 70°C) and Industrial
temperature (-40° to 85°C) variants are supported.
BLOCK DIAGRAM
REFINAB (15)
REFINCD (10)
DIN (4)
FS (7)
SCLK (5)
NCS (6)
WM2614
16-BIT
SHIFT
REGISTER
AND
CONTROL
LOGIC
data
DAC A
14-BIT
DATA AND
CONTROL
HOLDING
LATCH
AVDD
(16)
DVDD
(1)
REFERENCE
INPUT BUFFER
X1
12-BIT
DAC
LATCH
DAC
OUTPUT
BUFFER
X2
(14) OUTA
2-BIT
CONTROL
LATCH
POWERDOWN/
SPEED
CONTROL
POWER-ON
RESET
(9)
AGND
(8)
DGND
DAC B
DAC C
DAC D
(3)
NLDAC
(2)
NPD
(13) OUTB
(12) OUTC
(11) OUTD
TYPICAL PERFORMANCE
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
AVDD = DVDD = 5V, VREF = 2.048V, Speed = Fast mode, Load = 10k/100pF
512
1024
1536
2048
2559
DIGITAL CODE
3071
3583
4095
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
http://www.wolfson.co.uk
Production Data Datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics’ terms and conditions.
2614Mastera.doc June 18, 1999 14:36
©1999 Wolfson Microelectronics Ltd.

1 page




WM2614 pdf
Production Data Rev 1.0
WM2614
Test Conditions:
RL = 10k, CL = 100pF. AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over
recommended operating free-air temperature range (unless noted otherwise).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
MAX
UNIT
Reference
Reference input resistance
Reference input capacitance
RREFIN
CREFIN
10 M
5 pF
Reference feedthrough
Reference input bandwidth
Digital Inputs
VREF = 1VPP at 1kHz
+ 1.024V dc, DAC code 0
VREF = 0.2VPP + 1.024V dc
DAC code 2048
Slow
Fast
-75
0.5
1
dB
MHz
MHz
High level input current
Low level input current
Input capacitance
IIH Input voltage = DVDD
IIL Input voltage = 0V
CI
1 µA
-1 µA
3 pF
Notes:
1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full scale errors).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in
digital input code.
3. Zero code error is the voltage output when the DAC input code is zero.
4. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error.
5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the proportion of this signal imposed
on the zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are normalised to VREF.
7. Output load regulation is the difference between the output voltage at full scale with a 10kload and 2kload. It is expressed as a
percentage of the full scale output voltage with a 10kload.
8. IDD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V supply current will increase.
9. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test.
10. Slew rate results are for the lower value of the rising and falling edge slew rates.
11. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges.
Limits are ensured by design and characterisation, but are not production tested.
12. SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fs.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
5

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