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WM8143-12 데이터시트 PDF




Wolfson Microelectronics plc에서 제조한 전자 부품 WM8143-12은 전자 산업 및 응용 분야에서
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부품번호 WM8143-12 기능
기능 12-bit/4MSPS CCD Signal Processor
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WM8143-12 데이터시트, 핀배열, 회로
WM8143-12
12-bit/4MSPS CCD Signal Processor
Production Data Nov. 1999 Rev 4
Description
The WM8143-12 integrates the analogue signal
conditioning required by CCD sensors with a 12-bit ADC.
The WM8143-12 requires minimal external circuitry and
provides a cost-effective sensor to digital domain system
solution.
Each of the three analogue conditioning channels
includes reset level clamp, CDS, fine offset level shifting
and programmable gain amplification. The three channels
are multiplexed into the ADC. The output from the ADC is
fed to the output bus pins OP[11:0] via a 12/8 bit
multiplexer, enabled by the OEB signal.
The flexible output architecture allows twelve-bit data to
be accessed either on a twelve-bit bus or via a time-
multiplexed eight-bit bus. The WM8143-12 can be
configured for pixel-by-pixel or line-by-line multiplexing
operation. Reset level clamp and/or CDS features can be
optionally bypassed. The device configuration is
programmed either via a simple serial interface or via an
eight-bit parallel interface.
The serial/parallel interfaces of the WM8143-12 are
control compatible with those of the WM8144-10 and
WM8144-12.
Features
Reset level clamp
Correlated double sampling (CDS)
Fine offset level shifting
Programmable gain amplification
12-bit ADC with maximum 4 MSPS
Simple clocking scheme
Control by serial or parallel interface
Time multiplexed eight-bit data output mode
32 pin TQFP package
Interface compatible with WM8144-10 and
WM8144-12
Applications
Flatbed scanners
Sheet feed scanners
Film scanners
CCD sensor interfaces
Contact image sensor (CIS) interfaces
Block Diagram
VRLC
VRU VRT
VRB
VMID
VSMP MCLK RLC
AGND DGND DVDD AVDD
VMID
RINP
GINP
BINP
CL RS VS
S/H
S/H
CDS
S/H
S/H
CDS
MUX
PGA
5-BIT REG
PGA
5-BIT REG
S/H
S/H
CDS
PGA
5-BIT REG
TIMING CONTROL
OFFSET
++
8-BIT +
SIGN DAC
VMID
OFFSET
++
8-BIT +
SIGN DAC
VMID
OFFSET
++
8-BIT +
SIGN DAC
VMID
M
U
X
WM8143-12
12-bit
ADC
12/8
MUX
CONFIGURABLE
SERIAL/PARALLEL
CONTROL INTERFACE
OEB
OP[11:0]
SDI / DNA
SCK / RNW
SEN / STB
NRESET
Production Data datasheets contain
final specifications current on
publication date. Supply of products
conforms to Wolfson
Microelectronics' terms and
conditions.
Wolfson Microelectronics ©1999 Wolfson Microelectronics Ltd.
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386 Fax +44 (0) 131 667 5176
www: http://www.wolfson.co.uk




WM8143-12 pdf, 반도체, 판매, 대치품
WM8143-12
Production Data
Test Characteristics
AVDD = DVDD = 4.75V to 5.25V, AGND = DGND = 0V … TA = 0oC to +70oC, MCLK = 8MHz, unless otherwise stated
PARAMETER
SYMBOL
TEST
CONDITIONS
Full Scale Voltage Error
Differential Non Linearity
DNL
Integral Non Linearity
INL
12-bit ADC performance including CDS, PGA and Offset Functions
NO MISSING CODES GUARANTEED
Resolution
AVDD = DVDD = 5V
Maximum Sampling Rate
AVDD = DVDD = 5V
Zero Scale Transition Error
Voltage at VINP
DAC Code = 000H,
AVDD = DVDD = 5V,
measured relative to
VRB
Full Scale Transition Error
Voltage at VINP
DAC Code = 000H,
AVDD = DVDD = 5V,
measured relative to
VRT
Differential Non Linearity
DNL
AVDD = DVDD = 5V
PGA Gain
Monotonicity Guaranteed
Red Channel Max Gain
Gr Mode 1
AVDD = DVDD = 5V
Green Channel Max Gain
Gg
Blue Channel Max Gain
Gb
Switching Characteristics
MCLK Period
tPER
MCLK High
tCKH
MCLK Low
tCKL
Data Set-up Time
tDSU
Data Hold Time
tDH
Output Propagation Delay
Output Enable Time
tPD
tPZE
IOH = 1mA, IOL = 1mA
Output Disable Time
tPEZ
Serial Interface
SCK Period
tSPER
SCK High
tSCKH
SCK Low
tSCKL
SDI Set up Time
tSSU
SDI Hold Time
tSH
Set up Time - SCK to SEN
tSCE
MIN
0
12
4
7.5
7.5
7.5
125
37.5
37.5
10
10
125
37.5
37.5
10
10
20
TYP
0.1
0.25
± 25
± 25
8
8
8
MAX
20
0.5
1
UNIT
mV
LSB
LSB
±100
Bits
MSPS
mV
±100
mV
+1.5
LSB
Times
Times
Times
ns
ns
ns
ns
ns
75 ns
50 ns
25 ns
ns
ns
ns
ns
ns
ns
Wolfson Microelectronics
PD. Rev 4 Nov. 99
4

4페이지










WM8143-12 전자부품, 판매, 대치품
Production Data
WM8143-12
PIN NAME
28 MCLK
TYPE
Digital IP
29
DGND
Digital supply
30 OP[0] Digital OP
31 OP[1] Digital OP
32
DVDD
Digital supply
Typical Performance
AVDD = DVDD = 5V, TA = 25oC
WM8143-12 DNL
2
DESCRIPTION
Master clock. This clock is applied at eight, six, three or two times the input pixel rate
depending on the operational mode. MCLK is divided internally to define the ADC
sample rate and to provide the clock source for digital logic
Digital ground (0V)
See description for pins 1-10
See description for pins 1-10
Positive digital supply (5V)
1.5
1
0.5
0
-0.5
-1
-1.5
-2
0
8.25
8
7.75
7.5
7.25
7
6.75
6.5
6.25
6
5.75
5.5
5.25
5
4.75
4.5
4.25
4
3.75
3.5
3.25
3
2.75
2.5
2.25
2
1.75
1.5
1.25
1
0.75
0.5
0.25
0
0
512
1024
1536
2048
2560
3072
3584
4096
ADC Code
PGA Gain Code vs Actual Gain
RED
GREEN
BLUE
123456789
Actual Gain
Wolfson Microelectronics
7
PD. Rev 4 Nov. 99

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