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WM8144 데이터시트 PDF




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부품번호 WM8144 기능
기능 Integrated 10-bit Data Acquisition system for Imaging Applications
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WM8144 데이터시트, 핀배열, 회로
WM8144-10
Production Data
October 1997 Rev. 3.0
Integrated 10-bit Data Acquisition system for
Imaging Applications
Description
Features
WM8144-10 integrates the analogue signal conditioning
required by CCD sensors with a 10-bit ADC and optional
pixel-by-pixel image compensation. WM8144-10 requires
minimal external circuitry and provides a cost effective
sensor-to-digital domain system solution.
Each analogue conditioning channel provides reset level
clamp, CDS, fine offset level shifting and gain
amplification. The three channels are multiplexed into the
ADC. Output from the ADC can either be direct or passed
through a digital post-processing function. The post-
processing provides compensation for variations in offset
and shading on a pixel-by-pixel basis.
• Reset level clamp
• Correlated Double Sampling (CDS)
• Fine offset level shifting
• Programmable Gain Amplification
• 10-Bit ADC with maximum 6 MSPS
• Digital post-processing for pixel-by-pixel
image compensation
• Simple clocking scheme
• Control by serial or parallel interface
• Time-multiplexed eight-bit data output mode
• 48 pin TQFP package
• Pin compatible with WM8144-12
The flexible output architecture allows ten-bit data to be
accessed either on a ten-bit bus or via a time-multiplexed
eight-bit bus. The WM8144-10 can be configured for pixel-
by-pixel or line-by-line multiplexing operation. Reset level
clamp and/or CDS features can be optionally bypassed.
Device configuration is either by a simple serial or eight-
bit parallel interface.
Applications
• Document scanners
• CCD sensor interfaces
• Contact image sensor (CIS) interfaces
Block Diagram
VRLC
VRU VRT
VRB VRL
VMID
VSMP MCLK RLC
AVDD AGND DVDD1 DVDD2 DGND
VMID
RINP
GINP
BINP
MUX
CL RS VS
S/H
S/H
PGA
CDS
5-BIT REG
S/H
S/H
PGA
CDS
5-BIT REG
S/H
S/H
PGA
CDS
5-BIT REG
TIMING CONTROL
OFFSET
8-BIT + SIGN
DAC
VMID
OFFSET
8-BIT + SIGN
DAC
VMID
OFFSET
8-BIT + SIGN
DAC
VMID
WM8144-10
EXTERNAL
DATA STORE
INTERFACE
M
U
X
10 BIT
ADC
IMAGE
COMPENSATION
PROCESSING
10/8
MUX
CONFIGURABLE
SERIAL/PARALLEL
CONTROL INTERFACE
CC[2:0]
DV
CDATA(7:0)
ORNG
OEB
OP[9:0]
PNS
SDI / DNA
SCK / RNW
SEN / STB
NRESET
Production Data data sheets contain fi-
nal specifications current on publication
date. Supply of products conforms to
Wolfson Microelectronics standard terms
and conditions
Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK
Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176
www: http://www.wolfson.co.uk
© 1997 Wolfson Microelectronics




WM8144 pdf, 반도체, 판매, 대치품
WM8144-10
Electrical Characteristics (Contd.)
VDD = 4.75V to 5.25V, GND = 0 V, ........TA = 0oC to +70oC, MLCK = 12MHz unless otherwise stated.
PARAMETER
10-Bit ADC
Resolution
Maximum Sampling Rate
TEST CONDITIONS MIN
VDD = 5V
VDD = 5V
10
6
TYP
MAX UNIT
Bits
MSPS
Full Scale Transition Error Voltage at
VINP
DAC Code = 000H, VDD=5V,
measured relative to VRT
+/-50
+/-200 mV
Zero Scale Transition Error Voltage at
VINP
DAC Code = 000H, VDD=5V,
measured relative to VRB
Differential Non Linearity
Number of missing codes
PGA Gain
Red Channel Max. Gain, Note 1
Green Channel Max. Gain, Note 2
Blue Channel Max. Gain, Note 2
Red Channel Max. Gain, Note 2
Green Channel Max. Gain, Note 2
Blue Channel Max. Gain, Note 2
DNL VDD = 5V
-1
Gr12 MCLK=12MHz; VDD=5V
Gg12 Mode=1
Gb12
Gr8 MCLK=8MHz; VDD=5V
Gg8 Mode=1
Gb8
4
7
7
6
7
7
Note 1: Guaranteed monotonic up to PGA Gain code 0Fh
Note 2: Guaranteed monotonic up to PGA Gain code 1Fh
+/-50
+/-200 mV
+1.25 LSB
0 Code
Times
Times
Times
Times
Times
Times
Wolfson Microelectronics
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WM8144 전자부품, 판매, 대치품
WM8144-10
Pin Descriptions (contd.)
Pin No.
8
9
10
11
Name
CC[2]
CC[1]
CC[0]
ORNG
Type
Digital OP
Digital OP
Digital OP
Digital OP
25 OEB Digital IP
7 DV
Digital OP
12 NRESET Digital IP
Description
Colour code outputs. These outputs indicate from which channel the
current output sample was taken (R = 00X, G = 01X, B = 10X).
Two codes are provided per channel.
Out-of-range signal, active high. This signal indicates that the current
output pixel has exceeded the maximum or minimum achievable
somewhere within the pixel processing.
Output tri-state control, all outputs (OP[9:0], DV, ORNG, CC[2:]) enabled
when OEB=0
Data valid output, active low.
Reset input, active low. This signal forces a reset of all internal registers.
24 PNS
Digital IP
Control interface parallel (high) or serial (low, default)
27
SDI/DNA Digital IP
Serial Interface: serial interface input data signal
Parallel interface: high = data, low = address
28
SCK/RNW Digital IP
Serial Interface: serial interface clock signal
Parallel interface: high = OP[9:2] is output, low = OP[9:2] is input bus
26
SEN/STB Digital IP
Serial Interface: enable, active high
Parallel interface: strobe, active low
30
DVDD1
Digital supply Positive Digital Supply (5V)
4
DVDD2
Digital supply Positive Digital Supply (5V)
41
DGND
Digital supply Digital ground (0V)
17
AVDD
Analogue supply Positive Analogue supply (5V)
18
AGND
Analogue supply Analogue Ground (0V)
5 NC
Unused
Pin must be left unconnected
6 NC
Unused
Pin must be left unconnected
Wolfson Microelectronics
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