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PDF WM8146 Data sheet ( Hoja de datos )
| Número de pieza | WM8146 | |
| Descripción | 12-bit(8+4-bit) Linear Sensor Image Processor | |
| Fabricantes | Wolfson Microelectronics plc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de WM8146 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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WM8146
12-bit (8+4-bit) Linear Sensor Image Processor
Product Preview, January 2000 Rev 1.1
DESCRIPTION
The WM8146 is a 12-bit analogue front end/digitiser IC,
which processes and digitises the analogue output signals
from linear CCD sensors at pixel sample rates of up to
6MSPS.
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset adjust functions. The output from each of these
channels is time multiplexed into a single high-speed 12-bit
Analogue to Digital Converter. The digital output data is
available in 8+4-bit wide multiplexed format, with no missing
codes.
The WM8146 is controlled via a configurable serial
interface, which is compatible with all of Wolfson’s imaging
devices.
Powered from an analogue supply voltage of 5V and a
digital interface supply of either 5V or 3.3V, the WM8146
typically only consumes 175mW when operating from 5V
supplies.
FEATURES
• No missing codes guaranteed
• 6MSPS sample rate
• Colour pixel by pixel or line by line sampling
• Monochrome sampling
• Selectable reset level clamp voltage
• Pixel by pixel or line by line clamping
• Correlated double sampling
• 5-bit programmable gain amplifier
• 8-bit + sign offset adjustment
• 5V or 3.3V digital interface compatibility
• Serial control interface
• 28-pin SOIC package
APPLICATIONS
• Flatbed scanners
• Multi-function peripherals
• Copier scanners
• CCD sensor interfaces
BLOCK DIAGRAM
VRLC
(26)
AVDD VRT
(21) (24)
VRB
(23)
VMID AGND1 AGND2
(25) (22) (2)
VSMP MCLK
(5) (7)
RLC
(6)
DGND
(8)
DVDD1
(3)
DVDD2
(10)
VMID
RINP (1)
GINP(28)
BINP(27)
MUX
CL RS VS
S/H
S/H
CDS
PGA
5-BIT REG
S/H
S/H
CDS
PGA
5-BIT REG
S/H
S/H
CDS
PGA
5-BIT REG
TIMING CONTROL
OFFSET
++
8-BIT +
SIGN DAC
VMID
OFFSET
++
8-BIT +
SIGN DAC
VMID
OFFSET
++
8-BIT +
SIGN DAC
VMID
M
U
X
WM8146
12-bit
ADC
8+4
MUX
CONFIGURABLE
SERIAL CONTROL
INTERFACE
(4) OEB
(13) OP[0]
(14) OP[1]
(15) OP[2]
(16) OP[3]
(17) OP[4]
(18) OP[5]
(19) OP[6]
(20) OP[7]
(11)SDI
(12)SCK
(9) SEN
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
http://www.wolfson.co.uk
Product Preview data sheets contain
specifications for products in the formative
phase of development. These products may
be changed or discontinued without notice.
1999 Wolfson Microelectronics Ltd.
1 page  
Product Preview
WM8146
Test Conditions
AVDD = DVDD1 = DVDD2 =4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated.
PARAMETER
Supply Currents
Total supply current − active
Supply current − full power down
mode
SYMBOL
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
35 mA
5 mA
INPUT VIDEO SAMPLING
tPER
tMCLKH tMCLKL
MCLK
VSMP
INPUT
VIDEO
tVSMPSU
tVSMPH
tVSU
tVH
tRSU
tRH
Figure 1 Input Video Timing
Test Conditions
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated
PARAMETER
MCLK period
SYMBOL
tPER
TEST CONDITIONS
MIN
83.3
TYP
MCLK high period
tMCLKH
37.5
MCLK low period
tMCLKL
37.5
VSMP set-up time
tVSMPSU
10
VSMP hold time
tVSMPH
10
Video level set-up time
tVSU
10
Video level hold time
tVH
15
Reset level set-up time
tRSU
10
Reset level hold time
tRH
15
Notes: 1.
2.
tVSU and tRSU denote the set-up time required after the input video signal has settled.
Parameters are measured at 50% of the rising/falling edge.
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
OUTPUT DATA TIMING
MCLK
OP[7:0]
Figure 2 Output Data Timing
WOLFSON MICROELECTRONICS LTD
tPD
PP Rev 1.1 January 2000
5
5 Page 
Product Preview
WM8146
internal signals to control the sampling of the video signal. MCLK to VSMP ratios and maximum
sample rates for the various modes are shown in Table 1.
POWER SUPPLY
The WM8146 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface)
supplies.
OPERATING MODES
Table 1 summarises the most commonly used modes, the clock waveforms required and the register
contents required for CDS and non-CDS operation.
MODE
1
2
3
4
5
6
DESCRIPTION
Colour
Pixel-by-Pixel
Monochrome/
Colour
Line-by-Line
Fast
Monochrome/
Colour
Line-by-Line
Maximum
speed
Monochrome/
Colour
Line-by-Line
Slow Colour
Pixel-by-Pixel
Slow
Monochrome/
Colour
Line-by-Line
CDS
AVAILABLE
MAX
SAMPLE
RATE
Yes 2MSPS
Yes 2MSPS
Yes 4MSPS
No 6MSPS
Yes 1.5MSPS
Yes 1.5MSPS
SENSOR
INTERFACE
DESCRIPTION
The 3 input channels
are sampled in
parallel. The signal is
then gain and offset
adjusted before being
multiplexed into a
single data stream and
converted by the ADC,
giving an output data
rate of 6MSPS max.
As mode 1 except:
Only one input
channel at a time
is continuously
sampled.
Identical to mode 2
Identical to mode 2
Identical to mode 1
Identical to mode 2
TIMING
REQUIRE-
MENTS
MCLK max =
12MHz
MCLK:VSMP
ratio is 6:1
MCLK max =
12MHz
MCLK:VSMP
ratio is 6:1
MCLK max =
12MHz
MCLK:VSMP
ratio is 3:1
MCLK max =
12MHz
MCLK:VSMP
ratio is 2:1
MCLK max =
12MHz
MCLK:VSMP
ratio is
2n:1, n ≥ 4
MCLK max =
12MHz
MCLK:VSMP
ratio is
2n:1, n ≥ 4
REGISTER
CONTENTS
WITH
CONTROL
BIT CDS=1
SetReg1:
03(hex)
SetReg1:
07(hex)
SetReg3 bits
7:6
determine
which input is
to be
sampled
Identical to
mode 2 plus
SetReg3: bits
5:4 must be
set to 0(hex)
CDS not
possible
Identical to
mode 1
Identical to
mode 2
REGISTER
CONTENTS
WITH
CONTROL
BIT CDS=0
SetReg1:
01(hex)
SetReg1:
05(hex)
SetReg3
bits 7:6
determine
which input
is to be
sampled
Identical to
mode 2
SetReg1:
45(hex)
SetReg3
bits 7:6
determine
which input
is to be
sampled
Identical to
mode 1
Identical to
mode 2
Table 1 WM8146 Operating Modes
WOLFSON MICROELECTRONICS LTD
PP Rev 1.1 January 2000
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet WM8146.PDF ] | |
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