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부품번호 | WM8729 기능 |
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기능 | 24-bit/ 192kHz Stereo DAC | ||
제조업체 | Wolfson Microelectronics plc | ||
로고 | |||
전체 15 페이지수
DESCRIPTION
The WM8729 is a high performance stereo DAC designed
for audio applications such as DVD, home theatre systems,
and digital TV. The WM8729 supports data input word
lengths from 16 to 24-bits and sampling rates up to 192kHz.
The WM8729 consists of a serial interface port, digital
interpolation filters, multi-bit sigma delta modulators and
stereo DAC in a small 16-pin SOIC package.
The WM8729 has a hardware control interface for selection
of audio data interface format and de-emphasis.
The WM8729 is an ideal device to interface to AC-3,
DTS, and MPEG audio decoders for surround sound
applications, or for use in DVD players, including supporting
the implementation of 2 channels at 192kHz for high-end
DVD-Audio applications.
WM8729
24-bit, 192kHz Stereo DAC
Product Preview, Rev 1.2, April 2001
FEATURES
• Stereo DAC
• Audio Performance
- 106dB SNR (‘A’ weighted @ 48kHz) DAC
- -97dB THD
• DAC Sampling Frequency: 8kHz – 192kHz
• Pin Selectable Audio Data Interface Format
- I2S or Right Justified
• 3.0V - 5.5V Supply Operation
• 16-pin SOIC Package
• Exceeds Dolby Class A Performance Requirements
APPLICATIONS
• DVD-Audio and DVD ‘Universal’ Players
• Home theatre systems
• Digital TV
• Digital broadcast receivers
BLOCK DIAGRAM
FORMAT MUTEB DEM
CONTROL INTERFACE
WM8729
BCKIN
LRCIN
DIN
SERIAL
INTERFACE
MUTE
MUTE
DIGITAL FILTERS
SIGMA
DELTA
MODULATOR
SIGMA
DELTA
MODULATOR
RIGHT
DAC
LOW
PASS
FILTER
VOUTR
LEFT
DAC
LOW
PASS
FILTER
VOUTL
MCLK
AVDD DVDD
VMID
VREFP VREFN AGND DGND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
www.wolfsonmicro.com
Product Preview data sheets contain
specifications for products in the formative
phase of development. These products may
be changed or discontinued without notice.
2001 Wolfson Microelectronics Ltd.
WM8729
Product Preview
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Digital supply range
Analogue supply range
Ground
Difference DGND to AGND
Analogue supply current
Digital supply current
Analogue supply current
Digital supply current
SYMBOL
DVDD
AVDD
AGND, DGND
TEST CONDITIONS
AVDD = 5V
DVDD = 5V
AVDD = 3.3V
DVDD = 3.3V
MIN
3.0
3.0
-0.3
TYP
0
0
19
8
18
4
MAX
5.5
5.5
+0.3
UNIT
V
V
V
V
mA
mA
mA
mA
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP MAX
Digital Logic Levels (TTL Levels)
Input LOW level
VIL
0.8
Input HIGH level
VIH
2.0
Output LOW
VOL IOL = 1mA
AGND + 0.3V
Output HIGH
VOH
IOH = 1mA
AVDD - 0.3V
Analogue Reference Levels
Reference voltage
VMID
(VREFP - (VREFP - (VREFP -
VREFN)/2 - VREFN)/2 VREFN)/2 +
50mV
50mV
Potential divider resistance
RVMID
12k
DAC Output (Load = 10k ohms. 50pF)
0dBFs Full scale output voltage
At DAC outputs
1.1 x
AVDD/5
SNR (Note 1,2,3)
A-weighted,
100 106
@ fs = 48kHz
SNR (Note 1,2,3)
A-weighted
106
@ fs = 96kHz
SNR (Note 1,2,3)
A-weighted
106
@ fs = 192kHz
SNR (Note 1,2,3)
A-weighted,
105
@ fs = 48kHz
AVDD, DVDD = 3.3V
SNR (Note 1,2,3)
A-weighted
103
@ fs = 96kHz
AVDD, DVDD = 3.3V
SNR (Note 1,2,3)
Non ‘A’ weighted @ fs
= 48kHz
106
THD (Note 1,2,3)
1kHz, 0dBFs
-97
THD+N (Dynamic range, Note 2)
1kHz, -60dBFs
100
106
DAC channel separation
100
Analogue Output Levels
Output level
Load = 10k ohms,
0dBFS
1.1
Load = 10k ohms,
0dBFS,
(AVDD = 3.3V)
0.726
Gain mismatch
channel-to-channel
±1
UNIT
V
V
V
V
V
ohms
Vrms
dB
dB
dB
dB
dB
dB
dB
dB
dB
VRMS
VRMS
%FSR
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
4
4페이지 WM8729
Product Preview
DEVICE DESCRIPTION
INTRODUCTION
The WM8729 is a high performance DAC designed for digital consumer audio applications. Its
range of features make it ideally suited for use in DVD players, AV receivers and other high end
consumer audio equipment.
The WM8729 is a complete 2-channel stereo audio digital-to-analogue converter, including digital
interpolation filter, multi-bit sigma delta with dither, and switched capacitor multi-bit stereo DAC
and output smoothing filters. It is fully compatible and an ideal partner for a range of industry
standard microprocessors, controllers and DSPs.
Control of internal functionality of the device is provided by hardware control (pin programmed).
Operation using master clocks of 256fs, 384fs, 512fs or 768fs is provided, selection between
clock rates being automatically controlled. Sample rates (fs) from less than 8ks/s to 96ks/s are
allowed, provided the appropriate system clock is input. Support is also provided for up to 192ks/s
using a master clock of 128fs or 192fs.
The audio data interface supports right justified or I2S (Philips left justified, one bit delayed)
interface formats.
The device is packaged in a small 16-pin SOIC.
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock
to which all audio data processing is synchronised. This clock is often referred to as the audio
system’s Master Clock. The external master clock can be applied directly through the MCLK input
pin with no configuration necessary for sample rate selection.
Note that on the WM8729, MCLK is used to derive clocks for the DAC path. The DAC path
consists of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In
a system where there are a number of possible sources for the reference clock it is recommended
that the clock source with the lowest jitter be used to optimise the performance of the DAC.
DIGITAL AUDIO INTERFACE
Audio data is applied to the internal DAC filters via the Digital Audio Interface. Two popular
interface formats are supported:
Right Justified mode
I2S mode
Both formats send the MSB first. The WM8729 supports word lengths of 16 or 24 bits in I2S
mode and 16 or 20 bits in right justified mode. In right justified and I2S modes, the digital audio
interface receives data on the DIN input. Audio Data is time multiplexed with LRCIN indicating
whether the left or right channel is present. LRCIN is also used as a timing reference to indicate
the beginning or end of the data words.
In right justified and I2S modes, the minimum number of BCKINs per LRCIN period is 2 times the
selected word length. LRCIN must be high for a minimum of word length BCKINs and low for a
minimum of word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the
above requirements are met.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.2 April 2001
7
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