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부품번호 | WM8734 기능 |
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기능 | STEREO AUDIO CODEC | ||
제조업체 | ETC | ||
로고 | |||
전체 30 페이지수
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Stereo Audio CODEC
WM8734
DESCRIPTION
The WM8734 is a low power stereo CODEC ideal for MD,
CD-RW machines and DAT recording applications.
Stereo line inputs are provided, along with a mute function
and programmable line level volume control.
Stereo 24-bit multi-bit sigma delta ADCs and DACs are
used with oversampling digital interpolation and decimation
filters.
Digital audio input word lengths from 16-32 bits and
sampling rates from 8kHz to 96kHz are supported.
Stereo audio line level outputs are provided along with anti-
thump mute and power up/down circuitry.
The device is controlled via a 2 or 3 wire serial interface.
The interface provides access to all features including level
controls, mutes, de-emphasis and power management
facilities. The device is available in 20-pin SSOP or 5x5mm
QFN packages.
FEATURES
• Audio Performance
− 90dB SNR (‘A’ weighted @ 48kHz) ADC
− 100dB SNR (‘A’ weighted @ 48kHz) DAC
− 2.7 – 3.6V Digital Supply Operation
− 2.7 – 3.6V Analogue Supply Operation
• ADC and DAC Sampling Frequency: 8kHz – 96kHz
• Selectable ADC High Pass Filter
• 2 or 3-Wire MPU Serial Control Interface
• Programmable Audio Data Interface Modes
− I2S, Left, Right Justified or DSP
− 16/20/24/32 bit Word Lengths
− Master or Slave Clocking Mode
• Stereo Audio Inputs and Outputs
• 20-Pin SSOP or 5x5mm QFN Package Options
APPLICATIONS
• CD and Minidisc Recorder
• MP3 Player / Recorder
BLOCK DIAGRAM
AVDD
VMID
AGND
RLINEIN
LLINEIN
CONTROL INTERFACE
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WM8734
VOL
+12 to -34.5dB,
1.5dB Steps
VOL
+12 to -34.5dB,
1.5dB Steps
CLKIN
DIVIDER
(Div x1, x2)
ADC
ADC
DIGITAL
FILTERS
DAC
MUTE
DAC
MUTE
DIGTAL AUDIO INTERFACE
ROUT
LOUT
WOLFSON MICROELECTRONICS LTD
www.wolfsonmicro.com
Advanced Information, November 2001, Rev 2.2
Copyright 2001 Wolfson Microelectronics Ltd.
WM8734
Advanced Information
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
MIN MAX
Digital supply voltage
-0.3V
+3.63V
Analogue supply voltage
-0.3V
+3.63V
Voltage range digital inputs
DGND -0.3V
DVDD +0.3V
Voltage range analogue inputs
AGND -0.3V
AVDD +0.3V
Master Clock Frequency (see Note 4)
40MHz
Operating temperature range, TA
Storage temperature prior to soldering
-10°C
+70°C
30°C max / 85% RH max
Storage temperature after soldering
-65°C
+150°C
Package body temperature (soldering 10 seconds)
+240°C
Package body temperature (soldering 2 minutes)
+183°C
Notes:
1. Analogue and digital grounds must always be within 0.3V of each other.
2. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD) or
digital supply buffer voltage (DBVDD).
3. The digital supply buffer voltage (DBVDD) must always be less than or equal to the analogue supply voltage (AVDD).
4. When CLKIDIV2=1.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supply range
Ground
Total analogue supply current
DCVDD
DBVDD
AVDD
DGND, AGND
IAVDD
Digital supply current
IDCVDD, IDBVDD
Standby Current Consumption
DCVDD, DBVDD,
AVDD = 3.3V
DCVDD, DBVDD
AVDD = 3.3V
2.7 3.3 3.6
V
2.7 3.3 3.6
V
2.7 3.3 3.6
V
0V
16 mA
8 mA
5 uA
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AI Rev 2.2 November 2001
4
4페이지 WM8734
MASTER CLOCK TIMING
MCLK
t MCLKL
t MCLKH
t MCLKY
Advanced Information
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
MCLK System clock pulse width high
TXTIH
MCLK System clock pulse width low
TXTIL
MCLK System clock cycle time
TXTIY
MCLK Duty cycle
TEST CONDITIONS
MIN
18
18
54
40:60
TYP
MAX
UNIT
60:40
ns
ns
ns
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
ADCLRC
WM8734
CODEC DACLRC
ADCDAT
DACDAT
DSP
ENCODER/
DECODER
Figure 2 Master Mode Connection
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AI Rev 2.2 November 2001
7
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