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WM8737 데이터시트 PDF




Wolfson Microelectronics plc에서 제조한 전자 부품 WM8737은 전자 산업 및 응용 분야에서
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부품번호 WM8737 기능
기능 STEREO ADC WITH MICROPHONE PREAMPLIFIER
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WM8737 데이터시트, 핀배열, 회로
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WM8737L
Stereo ADC with Microphone Preamplifier
DESCRIPTION
The WM8737L is a low power stereo audio ADC designed
specifically for portable applications such as minidisc and
memory audio / voice recorders.
The device offers three sets of stereo inputs, which can be
configured for line-level signals, for internal or table-top
microphones, or for DC measurement (battery monitor). A
programmable gain amplifier can be used for automatic
level control (ALC) with user programmable hold, attack and
decay times. The device also has a selectable high pass
filter to remove residual DC offsets.
If the signal source is mono, the WM8737L can run in mono
mode, saving power. It can also mix two channels to mono,
either in the analogue or the digital domain.
Master or slave mode clocking schemes are offered. Stereo
24-bit multi-bit sigma-delta ADCs are used with digital audio
output word lengths from 16-32 bits, and sampling rates
from 8kHz to 96kHz supported.
The device is controlled via a 2 or 3 wire serial interface.
The interface provides access to all features including gain
controls, analogue or digital mono mixing, and power
management facilities. The device is supplied in a leadless
5x5mm QFN package.
FEATURES
SNR 97dB (‘A’ weighted @ 3.3V, 48kHz, normal power
mode)
THD –85dB (at –1dB, 3.3V, normal power mode)
Complete Stereo / Mono Microphone Interface
- Programmable microphone preamp
- Automatic Level Control
- Low-noise microphone bias voltage
Configurable Power / Performance
Low Power Mode
- 8.5mW at AVDD = 1.8V (stereo, mic preamps off)
- 20mW at AVDD = 3.3V (stereo, mic preamps off)
Low Supply Voltages
- Analogue 1.8V to 3.6V
- Digital core: 1.42V to 3.6V
- Digital I/O: 1.8V to 3.6V
256fs / 384fs or USB master clock rates: 12MHz, 24MHz
Audio sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1,
48, 88.2, 96kHz generated internally from master clock
32-pin QFN package, 5 x 5 x 0.9mm
APPLICATIONS
Memory Audio / Voice Recorders
Minidisc Recorders
Portable Digital Music Systems
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
Advanced Information, May 2004, Rev 3.0
Copyright 2004 Wolfson Microelectronics plc




WM8737 pdf, 반도체, 판매, 대치품
WM8737L
PIN DESCRIPTION
PIN NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NAME
NC
SCLK
DBVDD
DCVDD
DGND
NC
MCLK
BCLK
ADCDAT
ADCLRC
MODE
AGND
MICBIAS
MVDD
AVDD
RACIN
RACOUT
RINPUT3
RINPUT2
RINPUT1
LINPUT1
LINPUT2
LINPUT3
LACOUT
LACIN
VMID
VREF
VREFP
VREFN
AGND
CSB
SDIN
Preliminary Technical Data
TYPE
No Connect
Digital Input
Supply
Supply
Supply
No Connect
Digital Input
Digital Input / Output
Digital Output
Digital Input / Output
Digital Input
Supply
Analogue Output
Supply
Supply
Analogue Input
Analogue Output
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Output
Analogue Input
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Supply
Digital Input
Digital Input / Output
DESCRIPTION
No Internal Connection
Control Interface Clock Input
Digital Buffer (I/O) Supply
Digital Core Supply
Digital Ground (return path for both DCVDD and DBVDD)
No Internal Connection
Master Clock
Audio Interface Bit Clock
ADC Digital Audio Data
Audio Interface Left / Right Clock
Control Interface Selection
Analogue Ground (return path for both AVDD and MVDD)
Microphone Bias
Microphone Bias and Microphone Pre-amplifier Positive Supply
Analogue Positive Supply
Right Channel DC Blocking Capacitor
Right Channel DC Blocking Capacitor
Right Channel Input 3
Right Channel Input 2
Right Channel Input 1
Left Channel Input 1
Left Channel Input 2
Left Channel Input 3
Left Channel DC Blocking Capacitor
Left Channel DC Blocking Capacitor
Midrail Voltage Decoupling Capacitor
Reference Voltage Decoupling Capacitor
Positive Reference Decoupling Connection
Negative Reference Decoupling Connection
Analogue Ground (return path for both AVDD and MVDD)
Chip Select / Device Address Selection
Control Interface Data Port
w
AI Rev 3.0 May 2004
4

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WM8737 전자부품, 판매, 대치품
Preliminary Technical Data
WM8737L
Test Conditions
DCVDD = 1.5V, AVDD = MVDD = 3.3V, TA = +25oC, 1kHz -0.5dBFS signal, Normal Power Mode, fs = 48kHz, PGA gain = 0dB,
24-bit audio data, unless otherwise stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNIT
Line Inputs (LINPUT1/2/3, RINPUT1/2/3) to ADC – MIC pre-amp BYPASSED
Full Scale Input Signal Level
AVDD = 3.3V
1.0 V rms
(for ADC 0dB Input at 0dB Gain)
AVDD = 1.8V
0.545
Signal to Noise Ratio
SNR
AVDD = 3.3V,
90
97
dB
(A-weighted)
Normal Power Mode
(Note 1)
AVDD = 2.7V,
95
Normal Power Mode
AVDD = 1.8V,
92
Normal Power Mode
AVDD = 3.3V,
95
Low Power Mode
AVDD = 2.7V,
93
Low Power Mode
AVDD = 1.8V,
90
Low Power Mode
Dynamic Range
DNR
-60dBFS,
90 97
dB
(A-weighted)
Normal Power Mode
(Note 2)
-60dBFS,
95
Low Power Mode
Total Harmonic Distortion
THD
-1dB input
-86 (0.007%)
dB
(Note 3)
-1dB input,
AVDD=1.8V
-81 (0.009%)
%
ADC Channel Separation
1kHz signal
105 dB
(Note 4)
Channel Matching
1kHz signal
0.2 dB
Programmable Gain Amplifier (PGA)
Programmable Gain
-97 0 30 dB
Programmable Gain Step Size
Monotonic
0.5 dB
Gain Error (Deviation from ideal
0.5dB/step gain characteristic)
1kHz signal
-0.2
0.2 dB
Input Resistance
0dB gain
30 k
30dB gain
1.9
Input Capacitance
16.9pF
pF
Automatic Level Control (ALC)
Typical Record Level
-18 -3 dB
Gain Hold Time (Note 5)
Gain Ramp-Up (Decay) Time
(Notes 6, 7)
tHLD 0, 2.67, 5.33, 10.67, … , 43691
MCLK = 12.288MHz
(time doubles with each step)
tDCY (Note 3)
33.6, 67.2, 134.4, … , 3441
(time doubles with each step)
ms
ms
Gain Ramp-Down (Attack) Time
(Notes 6, 7)
tATK
8.4, 16.8, 33.6, … , 8600
(time doubles with each step)
ms
w
AI Rev 3.0 May 2004
7

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