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부품번호 | PCK12429A 기능 |
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기능 | 25-400 MHz differential PECL clock generator | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 14 페이지수
INTEGRATED CIRCUITS
PCK12429
25–400 MHz differential PECL
clock generator
Product data
Supersedes data of 2002 Mar 15
2002 Jun 03
Philips
Semiconductors
Philips Semiconductors
25–400 MHz differential PECL clock generator
32-Pin LQFP
Product data
PCK12429
S_CLOCK 1
S_DATA 2
S_LOAD 3
PLL-VCC 4
PLL-VCC 5
N/C 6
N/C 7
XTAL1 8
32-LEAD LQFP
24 N/C
23 N[1]
22 N[0]
21 M[8]
20 M[7]
19 M[6]
18 M[5]
17 M[4]
SW01012
PIN DESCRIPTION
SYMBOL
XTAL1, XTAL2
S_LOAD (Int. pulldown)
S_DATA (Int. pulldown)
S_CLOCK (Int. pulldown)
P_LOAD (Int. pullup)
M[8:0] (Int. pullup)
N[1:0] (Int. pullup)
OE (Int. pullup)
FOUT, FOUT
TEST
VCC1 and VCCO
PLL_VCC
GND
FUNCTION
These pins form an oscillator when connected to an external series-resonant crystal.
This pin loads the configuration latches with the contents of the shift registers. The latches will be
transparent when this signal is HIGH, thus the data must be stable on the HIGH-to-LOW transition
of S_LOAD for proper operation.
This pin acts as the data input to the serial configuration shift registers.
This pin serves to clock the serial configuration shift registers. Data from S_DATA is sampled on the
rising edge.
This pin loads the configuration latches with the contents of the parallel inputs. The latches will be
transparent when this signal is LOW, thus the parallel data must be stable on the LOW-to-HIGH
transition of P_LOAD for proper operation.
These pins are used to configure the PLL loop divider. They are sampled on the LOW-to-HIGH
transition of P_LOAD, M[8] is the MSB, M[0] is the LSB.
These pins are used to configure the output divider modulus. They are sampled on the
LOW-to-HIGH transition of P_LOAD.
Active HIGH Output Enable. The Enable is synchronous to eliminate possibility of runt pulse
generation on the FOUT output.
These differential positive-referenced ECL signals (PECL) are the output of the synthesizer.
The function of this output is determined by the serial configuration bits T[2:0].
This is the positive supply for the internal logic and the output buffer of the chip, and is connected to
+3.3 V (VCC = PLL_VCC).
This is the positive supply for the PLL, and should be as noise-free as possible for low-jitter
operation. This supply is connected to +3.3 V (VCC = PLL_VCC).
These pins are the negative supply for the chip and are normally all connected to ground.
2002 Jun 03
4
4페이지 Philips Semiconductors
25–400 MHz differential PECL clock generator
Product data
PCK12429
SCLOCK
FREF
MCNT
PLL 12429
M COUNTER
VCO_CLK
0
1
SEL_CLK
SDATA
SHIFT
REG
14-BIT
T0
T1
T2
LATCH
Reset
SLOAD
PLOADB
DECODE
N DIVIDE
(2, 4, 8, 16)
FOUT
(VIA ENABLE GATE)
FDIV4
MCNT
LOW
FOUT
MCNT
FREF
HIGH
7
TEST
MUX
0
TEST
• T2 = T1 = 1. T0 = 0: Test Mode
• SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin.
PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.
Figure 2. Serial Test Clock Block Diagram
SW00730
DC CHARACTERISTICS (Tamb = 0 to 70 °C, VCC = 3.3 V ± 5%)
SYMBOL
PARAMETER
CONDITION
VIH Input HIGH Voltage
VIL Input LOW Voltage
IIN Input Current
VOH Output HIGH Voltage
TEST
VOL Output LOW Voltage
TEST
VOH Output HIGH Voltage
FOUT
FOUT
VOL Output LOW Voltage
FOUT
FOUT
ICC Power Supply Current
VCC1
PLL_VCC
NOTES:
1. Output levels will vary 1:1 with VCC0 variation.
2. 50 Ω to VCC – 2.0 V pulldown.
VCC = 3.3 V
VCC = 3.3 V
IOH = –0.8 mA
IOL = 0.8 mA
VCC0 = 3.3 V
(Notes 1 and 2)
VCC0 = 3.3 V
(Notes 1 and 2)
LIMITS
UNIT
MIN TYP MAX
2.0 — — V
— — 0.8 V
— — 1.0 mA
2.5 —
V
— — 0.4 V
2.17 — 2.50 V
1.41 — 1.76 V
85 100
— mA
15 20
2002 Jun 03
7
7페이지 | |||
구 성 | 총 14 페이지수 | ||
다운로드 | [ PCK12429A.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
PCK12429 | 25-400 MHz differential PECL clock generator | NXP Semiconductors |
PCK12429A | 25-400 MHz differential PECL clock generator | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |