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X1240 데이터시트 PDF




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부품번호 X1240 기능
기능 Real Time Clock/Calendar with EEPROM
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X1240 데이터시트, 핀배열, 회로
Preliminary Information
16K
X1240
2-Wire RTC
Real Time Clock/Calendar with EEPROM
FEATURES
• 2-Wire Interface interoperable with I2C.
—400kHz data transfer rate
• Secondary Power Supply Input with internal
switch-over circuitry.
• Year 2000 Compliant
• 2K bytes of EEPROM
—64 Byte Page Write Mode
—3 bit Block Lock
• Low Power CMOS
—<1µA Operating Current
—<3mA Active Current during Program
—<400µA Active Current during Data Read
• Single Byte Write Capability
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—1,000,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Package Options
—8-Lead SOIC Package, 8L TSSOP Package
DESCRIPTION
The X1240 is a Real Time Clock with clock/calendar
circuits. The dual port clock register allows the clock to
operate, without loss of accuracy, even during read and
write operations.
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
The device offers a backup power input pin. This
Vback pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational
from 1.8 to 5.5 volts.
The X1240 provides a 2K byte EEPROM array, giving
a safe, secure memory for critical user and configura-
tion data. This memory is unaffected by complete fail-
ure of the main and backup supplies.
BLOCK DIAGRAM
32.768kHz
X1
X2
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
SCL
SDA
Serial
Interface
Decoder
Control
Decode
Logic
8
Control
Registers
(EEPROM)
Status
Register
(SRAM)
16K
EEPROM
Array
©Xicor, Inc. 1994, 1995, 1996, 1997, 1998, 1999 Patents Pending
9900-3003.5 12/6/99 CM
1
Characteristics subject to change without notice




X1240 pdf, 반도체, 판매, 대치품
X1240
Table 1. Clock/Control Memory Map
Addr.
Type
Reg
Name
003F Status
0037
0036
0035
0034 RTC
0033 (SRAM)
0032
0031
0030
0011 Control
0010 (E2PROM)
SR
Y2K
DW
YR
MO
DT
HR
MN
SC
INT
BL
7
BAT
0
0
Y23
0
0
MIL
0
0
0
BP2
6
0
0
0
Y22
0
0
0
M22
S22
0
BP1
5
0
Y2K21
0
Y21
0
D21
H21
M21
S21
0
BP0
Bit
4
0
Y2K20
0
Y20
G20
D20
H20
M20
S20
0
0
3
0
Y2K13
0
Y13
G13
D13
H13
M13
S13
0
0
2
RWEL
0
DY2
Y12
G12
D12
H12
M12
S12
0
0
Range
1 0 (optional)
WEL RTCF
0 Y2K10 19/20
DY1 DY0 0-6
Y11 Y10 0-99
G11 G10 1-12
D11 D10 1-31
H11 H10 0-23
M11 M10 0-59
S11 S10 0-59
00
00h
00
00h
REAL TIME CLOCK REGISTERS
Year 2000 (Y2K)
The X1240 has a century byte that “rolls over” from 19
to 20 when the years byte changes from 99 to 00. The
Y2K byte can contain only the values of 19 or 20.
Day of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-... The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
Clock Default values define 0=Sunday.
Clock/Calendar Registers (YR, MO, DT, HR, MN, SC)
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is
1 to 31, MO (Month) is 1 to 12, YR (year) is 0 to 99.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC will use a
24-hour format. If the MIL bit is 0, the RTC will use 12-
hour format and bit H21 will function as an AM/PM
indicator with a ‘1’ representing PM. The clock defaults
to Standard Time with H21=0.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible
by 100 are not leap years, unless they are also divisi-
ble by 400. This means that the year 2000 is a leap
year, the year 2100 is not. The X1240 does not correct
for the leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the RTC area at
address 003FH. This is a volatile register only and is
used to control the WEL and RWEL write enable
latches, and read a Low Voltage Sense bit. This regis-
ter is logically seperated from both the array and the
Clock/Control Registers (CCR).
Table 2. Status Register (SR)
Addr
003Fh
Default
7
BAT
0
6
0
0
5 43 2 1 0
0 0 0 RWEL WEL RTCF
0 00 0 0 0
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from VBACK, not VCC. It is a read only bit and is set/
reset by hardware.
4

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X1240 전자부품, 판매, 대치품
X1240
Figure 5. Acknowledge Response From Receiver
SCL from Master
1
Data Output from
Transmitter
Data Output
from Receiver
Start
89
Acknowledge
Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 5.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
—The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
—All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
—The 2nd Data Byte of a Register Write Operation
(when only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
WRITE OPERATIONS
Byte Write
For a byte write operation, the device requires the
Slave Address Byte and the Word Address Bytes. This
gives the master access to any one of the words in the
array or CCR. (Note: Prior to writing to the CCR, the
master must write a 02h, then 06h to the status regis-
ter in preceding operations to enable the write opera-
tion. See “Writing to the Clock/Control Registers” on
page 6.) Upon receipt of each address byte, the
X1240 responds with an acknowledge. After receiving
both address bytes the X1240 awaits the eight bits of
data. After receiving the 8 data bits, the X1240 again
responds with an acknowledge. The master then ter-
minates the transfer by generating a stop condition.
The X1240 then begins an internal write cycle of the
data to the nonvolatile memory. During the internal
write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 6.
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X1240 will not initiate an internal
write cycle, and will continue to ACK commands.
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