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ZPSD402A1V-C-20JI PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ZPSD402A1V-C-20JI
기능 Low Cost Field Programmable Microcontroller Peripherals
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ZPSD402A1V-C-20JI 데이터시트, 핀배열, 회로
PSD4XX
ZPSD4XX
Low Cost Field Programmable Microcontroller Peripherals
NOT FOR NEW DESIGN
FEATURES SUMMARY
s Single Supply Voltage:
– 5 V±10% for PSD4XX
– 2.7 to 5.5 V for PSD4XX-V
s Up to 1 Mbit of UV EPROM
s Up to 16 Kbit SRAM
s Input Latches
s Programmable I/O ports
s Page Logic
s Programmable Security
Figure 1. Packages
PLDCC68 (J)
CLDCC68 (L)
TQFP68 (U)
January 2002
This is information on a product still in production but not recommended for new designs.
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ZPSD402A1V-C-20JI pdf, 반도체, 판매, 대치품
1.0
Introduction
Programmable Peripheral
PSD4XX Family
Field-Programmable Microcontroller Peripherals
The PSD4XX family is a microcontroller peripheral that integrates high-performance and
user-configurable blocks of EPROM, programmable logic, and SRAM into one part.
The PSD4XX products also provide a powerful microcontroller interface that eliminates the
need for external “glue logic”. The no “glue logic” concept provides a user-programmable
interface to a variety of 8- and 16-bit (multiplexed or non-multiplexed) microcontrollers that
is easy to use. The part’s integration, small form factor, low power consumption, and ease
of use make it the ideal part for interfacing to virtually any microcontroller.
The PSD4XX provides two Zero-power PLDs (ZPLD): a Decode PLD (DPLD) and a
General-purpose PLD (GPLD). A configuration bit (Turbo) can be set by the MCU, and will
automatically place the ZPLDs into Standby Mode if no inputs are changing. The ZPLDs are
designed to consume minimum power using Zero-power CMOS technology that uses only
10 µA (typical) standby current. Unused product terms are automatically disabled, also
reducing power, regardless of the Turbo bit setting.
The main function of the DPLD is to perform address decoding for the internal I/O ports,
EPROM, and SRAM. The address decoding can be based on up to 24 bits of address
inputs, control signals (RD, WR, PSEN, etc.), and internal page logic. The DPLD supports
separate program and data spaces (for 8031 compatible MCUs).
The General-purpose PLD (GPLD) can be used to implement various logic functions
defined by the user, such as:
State machines
Loadable counters and shift registers
Inter-processor mailbox
External control logic (chip selects, output enables, etc.).
The GPLD has access to up to 59 inputs, 118 product terms, 24 macrocells, and 24 I/O
pins.
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ZPSD402A1V-C-20JI 전자부품, 판매, 대치품
CONTROL
RD, WR
PROG.
BUS
INTRF
AD0 – AD15
ADIO
PORT
PC0 – PC7
PROG.
PORT
PORT
C
PD0 – PD7
PROG.
PORT
PORT
D
CLKIN
ADDRESS/DATA/CONTROL BUS
ZPLD
INPUT
BUS
PAGE
REG.
DECODE PLD
(DPLD)
(NOTE 1)
EPROM
SELECTS
SRAM
SELECT
PERIPHERAL
SELECTS
CSIOP
256K –1M BIT
EPROM
16 K BITS
SRAM
I/O
DECODER
(NOTE 1)
CLKIN
GENERAL PLD
(GPLD)
27PT
80PT
11PT
24 MACROCELLS
PORT A MACROCELLS
PORT B MACROCELLS
PORT E MACROCELLS
(NOTE 2)
MACROCELL FEEDBACK OR PORT INPUT
CLKIN
NOTES: 1. ZPLD INPUT BUS
– A1 = 36 + CLOCK = 37 INPUTS
– A2 = 58 + CLOCK = 59 INPUTS
2. PORT E MACROCELLS AVAILABLE ON A2 VERSIONS ONLY.
POWER
MANAGER
UNIT
VSTDBY
PROG.
PORT PA0 – PA7
PORT
A
PROG.
PORT PB0 – PB7
PORT
B
PROG.
PORT PE0 – PE7
PORT
E
GLOBAL
CONFIG.
&
SECURITY

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ZPSD402A1V-C-20J

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics
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ZPSD402A1V-C-20JI

Low Cost Field Programmable Microcontroller Peripherals

STMicroelectronics
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