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PDF AMD-8131BLC Data sheet ( Hoja de datos )
| Número de pieza | AMD-8131BLC | |
| Descripción | Hyper Transport PCI-X Tunnel | |
| Fabricantes | AMD | |
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24637 Rev 3.02 - August 10, 2004
AMD-8131TM PCI-X Tunnel Data Sheet
Cover page
AMD-8131TM HyperTransportTM PCI-X Tunnel
Data Sheet
1 Overview
The AMD-8131TM HyperTransportTM PCI-XTunnel (referred to as the IC in this document) is a
HyperTransport™ technology (referred to as link in this document) tunnel developed by AMD that provides
two PCI-X bridges.
1.1 Device Features
• HyperTransport technology tunnel with side A
and side B.
• Side A is 16 bits (input and output); side B is
8 bits.
• Either side may connect to the host or to a
downstream HyperTransport technology
compliant device.
• Each side supports HyperTransport technol-
ogy-defined reduced bit widths: 8-bit, 4-bit,
and 2-bit.
• Each side supports transfer rates of 1600,
1200, 800, and 400 mega-transfers per sec-
ond.
• Maximum bandwidth is 6.4 gigabytes per
second across side A (half upstream and half
downstream) and 3.2 gigabytes per second
across side B.
• Independent transfer rate and bit width
selection for each side.
• Link disconnect protocol supported.
• Two PCI-X (rev. 1.0) bridges: bridge A and
bridge B.
• Each bridge supports a 64-bit data bus.
• Each bridge supports operational modes of
PCI-X and legacy PCI revision 2.2 protocol.
• Bridges support 133, 100, and 66 MHz
transfer rates in PCI-X mode.
• Bridges support 66 and 33 MHz transfer
rates in PCI mode.
• Independent transfer rates and operational
modes for each bridge.
• Each bridge includes support for up to 5 PCI
masters with clock, request, and grant sig-
nals.
• Each bridge includes an IOAPIC with four
redirection registers. Legacy interrupt con-
troller and IOAPIC modes supported.
• SHPC-compliant hot plug controller and
support.
• 37.5 x 37.5 millimeter, 829-pin BGA package.
• 3.3 volt PCI-X signaling; 1.2 volt link signaling;
1.8 volt core.
AMD-8131TM Device
HyperTransportTM Side A
Side B HyperTransport
Host Link
Link Downstream
16 bits upstream,
tunnel
8 bits upstream,
Device
16 bits downstream
8 bits downstream
PCI-X
PCI-X
slots Bridge A Bridge B
slots
Figure 1: System block diagram.
1
1 page  
24637 Rev 3.02 - August 10, 2004
AMD-8131TM PCI-X Tunnel Data Sheet
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
System block diagram................................................................................................................... 1
Systemboard clocking. ................................................................................................................ 17
Correction for characterization. .................................................................................................. 18
System diagram for multiple hot plug slots on a bridge. ............................................................ 22
System diagram of PME# signals. .............................................................................................. 23
System diagram of M66EN signals. ........................................................................................... 23
Multi-slot hot plug enable/disable sequence............................................................................... 24
Single-slot hot plug system diagram........................................................................................... 25
Single-slot hot plug enable/disable sequence.............................................................................. 26
Single-slot hot plug M66EN connections. .................................................................................. 26
Hot plug serial interface connections.......................................................................................... 27
Configuration space. ................................................................................................................... 40
Ball designations. ........................................................................................................................ 77
Package mechanical drawing. ..................................................................................................... 82
NAND tree. ................................................................................................................................. 83
5
5 Page 
24637 Rev 3.02 - August 10, 2004
AMD-8131TM PCI-X Tunnel Data Sheet
Pin name and description
IO cell Power Normal Single slot HP
type plane During After During After
reset reset reset reset
[B, A]_REQ[4:0]#. PCI-X master request input signals.
A_REQ[2:0]# are used for test-mode selection; see section 9.
[B, A]_HPSOLC. Hot plug serial output latch clock (alternative
function to [B, A]_REQ4 selected by hot plug mode,
DevA:0x48[HPENA, HPENB]). See section 4.5.3.3 for details.
IO (See VDD33 REQs REQs [0]: [0]:
left) are are Low; Low;
inputs; inputs; [3:1]: [3:1]:
HP- HP- inputs; inputs;
SOLC: SOLC: HP- HP-
High High SOLC: SOLC:
High High
[B, A]_REQ64#. PCI-X request for 64-bit transfers. The IC
drives this signal to the asserted state while [B, A]_PRESET# is
asserted.
IO VDD33 Low 3-State Low Low
[B, A]_SERR#. PCI-X system error signal.
Input VDD33
Low Low
[B, A]_STOP#. PCI-X target abort signal. During reset, these
signals may be 3-state or they may be driven, based on the
requirements of the PCI-X initialization pattern.
IO VDD33 See left 3-State Low Low
[B, A]_TRDY#. PCI-X target ready signal. During reset, these
signals may be 3-state or they may be driven, based on the
requirements of the PCI-X initialization pattern.
IO VDD33 See left 3-State Low
Low
HPSIC. Hot plug serial input clock; see section 4.5.3.3 for details. IO (See VDD33
This signal is an input only while PWROK is low and an output at left)
all other times. As an input, it is used to specify the default state of
DevA:0x40[HPSSS#]. HPSSS# specifies if the IC supports a
single hot plug slot on the bridge without external isolation
switches. A weak resistor should be tied from this signal to
VDD33 or to ground.
High
High
High
High
HPSIL#. Hot plug serial input load; see section 4.5.3.3 for details. IO (See VDD33
This signal is an input while PWROK is low and an output at all left)
other times. As an input, it is used to specify if bridge B of the IC
is in hot plug mode or not; the latched state is available in
DevA:0x48[HPENB]. To specify that bridge B is in hot plug
mode, a weak resistor to VDD33 should be placed on this signal.
To specify that bridge B is not in hot plug mode, a weak pulldown
resistor to ground should be placed on this node. When neither
bridge A nor B are in hot plug mode, this signal is always driven
high.
High
High
High
High
HPSOC. Hot plug serial output clock; see section 4.5.3.3 for
details.
Output VDD33 High High High High
11
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