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기능 16-Bit Monolithic DIGITAL-TO-ANALOG CONVERTERS
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PCM55HP 데이터시트, 핀배열, 회로
® PCM54
PCM55
DESIGNED FOR AUDIO
16-Bit Monolithic
DIGITAL-TO-ANALOG CONVERTERS
FEATURES
q PARALLEL INPUT FORMAT
q 16-BIT RESOLUTION
q 15-BIT MONOTONICITY (typ)
q –92dB TOTAL HARMONIC DISTORTION
(K Grade)
q 3µs SETTLING TIME (Voltage Out)
DESCRIPTION
The PCM54 and PCM55 family of converters are
parallel input, fully monotonic, 16-bit digital-to-ana-
log converters that are designed and specified for
digital audio applications. These devices employ ul-
tra-stable nichrome (NiCr) thin-film resistors to pro-
vide monotonicity, low distortion, and low differential
linearity error (especially around bipolar zero) over
long periods of time and over the full operating
temperature.
These converters are completely self-contained with a
stable, low noise, internal, zener voltage reference;
high speed current switches; a resistor ladder
network; and a fast settling, low noise output opera-
tional amplifier all on a single monolithic chip. The
converters are operated using two power supplies that
q 96dB DYNAMIC RANGE
q ±3V or ±1mA AUDIO OUTPUT
q OPERATES ON ±5V (PCM55) TO ±12V
(PCM54) SUPPLIES
q 28-PIN DIP (PCM54)
q 24-LEAD SOIC (PCM55)
can range from ±5V (PCM55) to ±12V (PCM54).
Power dissipation with ±5V supplies is typically less
than 200mW. Also included is a provision for exter-
nal adjustment of the MSB error (differential linearity
error at bipolar zero, PCM54 only) to further improve
Total Harmonic Distortion (THD) specifications if
desired.
A current output (IOUT) wiring option is provided. This
output typically settles to within ±0.006% of FSR
final value in 350ns (in response to a full-scale change
in the digital input code).
The PCM54 is packaged in 28-pin plastic DIP pack-
age. The PCM55 is available in a 24-lead plastic mini-
flatpak.
Reference
Voltage
RF
Parallel
Digital
Input
16-Bit Ladder
Resistor Network
and
Current Switches
Output
Operational
Amplifier
Audio Output
(Voltage)
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1985 Burr-Brown Corporation
PDS-619B
Printed in U.S.A. August, 1998




PCM55HP pdf, 반도체, 판매, 대치품
DISCUSSION OF
SPECIFICATIONS
The PCM54 and PCM55 are specified to provide critical
performance criteria for a wide variety of applications. The
most critical specifications for a D/A converter in audio
applications are total harmonic distortion, differential linear-
ity error, bipolar zero error, parameter shifts with time and
temperature, and settling time effects on accuracy.
The PCM54 and PCM55 are factory-trimmed and tested for
all critical key specifications.
The accuracy of a D/A converter is described by the transfer
function shown in Figure 1. Digital input to analog output
relationship is shown in Table I. The errors in the D/A
converter are combinations of analog errors due to the linear
circuitry, matching and tracking properties of the ladder and
scaling networks, power supply rejection, and reference
errors. In summary, these errors consist of initial errors
including gain, offset, linearity, differential linearity, and
power supply sensitivity. Gain drift over temperature rotates
0000…0000
0000…0001
0111…1101
0111…1110
0111…1111
1000…0000
1000…0001
1111…1110
1111…1111
Offset
Drift
Gain
Drift
All Bits
On
Bipolar
Zero
–FSR/2
Analog Output
* See Table I for digital code definitions.
(+FSR/2) –1LSB
FIGURE 1. Input vs Output for an Ideal Bipolar D/A
Converter.
the line (Figure 1) about the bipolar zero point and offset
drift shifts the line left or right over the operating tempera-
ture range. Most of the offset and gain drift with temperature
or time is due to the drift of the internal reference zener
diode. The converter is designed so that these drifts are in
opposite directions. This way, the bipolar zero voltage is
virtually unaffected by variations in the reference voltage.
DIGITAL INPUT CODES
The PCM54 and PCM55 accept complementary digital
input codes in any of three binary formats (CSB, unipolar; or
COB, bipolar; or CTC, Complementary Two’s Comple-
ment, bipolar). See Table II.
ANALOG OUTPUT
Digital
Input
Codes
Complementary
Straight Binary
(CSB)
Complementary
Offset Binary
(COB)
Complementary
Two’s Complement
(CTS)(1)
0000H
7FFFH
8000H
FFFFH
+Full Scale
+1/2 Full Scale
+1/2 Full Scale
–1LSB
Zero
+Full Scale
Bipolar Zero
–1LSB
–Full Scale
–1LSB
–Full Scale
+Full Scale
Bipolar Zero
NOTE: (1) Invert the MSB of the COB code with an external inverter to obtain
CTC code.
TABLE II. Digital Input Codes.
BIPOLAR ZERO ERROR
Initial Bipolar Zero (BPZ) error (Bit 1 “ON” and all other
bits “OFF”) is the deviation from 0V out and is factory-
trimmed to typically ±10mV at +25°C.
DIFFERENTIAL LINEARITY ERROR
Differential Linearity Error (DLE) is the deviation from an
ideal 1LSB change from one adjacent output state to the
next. DLE is important in audio applications because exces-
sive DLE at bipolar zero (at the “major carry”) can result in
audible crossover distortion for low level output signals.
Initial DLE on the PCM54 and PCM55 is factory-trimmed
to typically ±0.001% of FSR. This error is adjustable to zero
using the circuit shown in the connection diagram (PCM54
only).
VOLTAGE OUTPUT MODE
Unipolar(1)
Analog Output
Digital Input Code
16-Bit
15-Bit
14-Bit
16-Bit
One LSB
0000H
FFFFH
(µV) 91.6 183 366 91.6
(V)
+5.99991
+5.99982
+5.99963
+2.99991
(V) 0 0 0 –3.0000
CURRENT OUTPUT MODE
Analog Output
Unipolar
Digital Input Code
16-Bit
15-Bit
14-Bit
16-Bit
One LSB
0000H
FFFFH
(µA)
(mA)
(mA)
0.031
–1.99997
0
0.061
–1.99994
0
0.122
–1.99988
0
0.031
–0.99997
+1.00000
NOTE: (1) +VCC must be at least +8.5VDC to allow output to swing to +6.0VDC.
TABLE I. Digital Input to Analog Output Relationship.
®
PCM54/55
4
Bipolar
15-Bit
183
+2.99982
–3.0000
Bipolar
15-Bit
0.061
–0.99994
+1.00000
14-Bit
366
+2.99963
–3.0000
14-Bit
0.122
–0.99988
+1.00000

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PCM55HP 전자부품, 판매, 대치품
INSTALLATION
CONSIDERATIONS
If the optional external MSB error circuitry is used (PCM54),
a potentiometer with adequate resolution and a TCR of
100ppm/°C or less is required. Also, extra care must be
taken to insure that no leakage path (either AC or DC) exists
to pin 27 (PCM54). If circuit is not used, pin 1 (PCM54)
should be terminated to common with a 0.01µF capacitor.
The PCM converter and the wiring to its connectors should
be located to provide the optimum isolation from sources of
RFI and EMI. The important consideration in the elimina-
tion of RF radiation or pickup is loop area; therefore, signal
leads and their return conductors should be kept close
together. This reduces the external magnetic field along with
any radiation. Also, if a signal lead and its return conductor
are wired close together, they represent a small flux-capture
cross section for any external field. This reduces radiation
pickup in the circuit.
APPLICATIONS
A sample/hold amplifier, or “deglitcher”, is required at the
output of the D/A converter for both the left and right
channel, as shown in Figure 7. The S/H amplifier for the left
channel is composed of A2, SW1, and associated circuitry. A2
is used as an integrator to hold the analog voltage in C1.
Since the source and drain of the FET switch operates at a
virtual ground when “C” and “B” are closed in the simple
mode, there is no increase in distortion caused by the
modulation effect of RON by the audio signal.
Figure 8 shows the deglitcher control signals for both the left
and right channels which are produced by the timing control
logic. A delay of 2.5µs (tω) is provided to eliminate the
glitch and allow the output of the PCM54-V to settle within
a small error band around its final value before connecting
it to the channel output.
Due to the fast settling time of the PCM54-V, it is possible
to minimize the delay between the left channel and right
channel outputs when using a single D/A converter for both
channels. This is important because the left and right chan-
nel data is recorded in phase and use of a slower D/A
converter would result in significant phase error at the
higher audio frequencies.
A low-pass filter is required at the S/H output to remove all
unwanted frequency components caused by the sampling
frequency as well as the discrete nature of the D/A converter
output. The filter must have a flat amplitude response over
the entire audio band (0 to 20kHz) and a very high attenu-
ation above 20kHz. Most previous digital audio circuits used
a high-order (9-13 pole) analog filter. However, the phase
response of an analog filter with these amplitude character-
istics is nonlinear and can disturb the pulse-shaped charac-
teristics of the transients contained in music.
RR
PCM54/55
Data to
DAC
Left Channel
Deglitcher Control
C
B
A
SW1
R
C1
A1
Left Channel Output to LPF
and Other Circuits
R
C C2
Right Channel
Deglitcher Control
B
A
SW2
A2
Right Channel Output to LPF
and Other Circuits
A LOW signal on the
deglitcher control closes switch “A”,
while a HIGH signal closes switch “B”.
A1, A2 ATE
OPA101 or OPA404
FIGURE 7. A Sample/Hold Amplifier (deglitcher) is Re-
quired at the Digital-to-Analog Output for Both
Left and Right Channels.
Data for DAC
Right Channel
Deglitcher Control
Left Channel
Deglitcher Control
44.1kHz
Right Channel Data N Left Channel Data N Right Channel Data N+1 Left Channel Data N+1
tS
tW
Delay Between Left and Right Channel
The deglitcher control signals are generated by the timing control logic. The fast settling time of the
PCM54/55 makes it possible to minimize the delay between left and right channels to approximately 4.5µs
which reduces phase error at the higher audio frequencies.
FIGURE 8. Timing Diagram for the Deglitcher Control Signals.
®
7 PCM54/55

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PCM55HP

16-Bit Monolithic DIGITAL-TO-ANALOG CONVERTERS

Burr-Brown Corporation
Burr-Brown Corporation

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