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부품번호 PCM56U 기능
기능 Serial Input 16-Bit Monolithic DIGITAL-TO-ANALOG CONVERTER
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PCM56U 데이터시트, 핀배열, 회로
® PCM56P
PCM56U
DESIGNED FOR AUDIO
Serial Input 16-Bit Monolithic
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q SERIAL INPUT
q –92dB MAX THD: FS Input, K Grade
q –74dB MAX THD: –20dB Input, K Grade
q 96dB DYNAMIC RANGE
q NO EXTERNAL COMPONENTS REQUIRED
q 16-BIT RESOLUTION
q 15-BIT MONOTONICITY, TYP
q 0.001% OF FSR TYP DIFFERENTIAL
LINEARITY ERROR
q 1.5µs SETTLING TIME, TYP: Voltage Out
q ±3V OR ±1mA AUDIO OUTPUT
q EIAJ STC-007-COMPATIBLE
q OPERATES ON ±5V TO ±12V SUPPLIES
q PINOUT ALLOWS IOUT OPTION
q PLASTIC DIP OR SOIC PACKAGE
DESCRIPTION
The PCM56 is a state-of-the-art, fully monotonic,
digital-to-analog converter that is designed and
specified for digital audio applications. This device
employs ultra-stable nichrome (NiCr) thin-film
resistors to provide monotonicity, low distortion, and
low differential linearity error (especially around
bipolar zero) over long periods of time and over the
full operating temperature.
This converter is completely self-contained with a
stable, low noise, internal zener voltage reference;
high speed current switches; a resistor ladder net-
work; and a fast settling, low noise output operational
amplifier all on a single monolithic chip. The
converters are operated using two power supplies that
can range from ±5V to ±12V. Power dissipation with
±5V supplies is typically less than 200mW. Also
included is a provision for external adjustment of the
MSB error (differential linearity error at bipolar zero)
to further improve total harmonic distortion (THD)
specifications if desired. Few external components
are necessary for operation, and all critical
specifications are 100% tested. This helps assure the
user of high system reliability and outstanding overall
system performance.
The PCM56 is packaged in a high-quality 16-pin
molded plastic DIP package or SOIC and has passed
operating life tests under simultaneous high-pressure,
high-temperature, and high-humidity conditions.
Reference
16-Bit
IOUT DAC
16-Bit Input Latch
RF
Audio
Output
16-Bit Serial-to-Parallel Conversion
Clock LE Data
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1987 Burr-Brown Corporation
PDS-700D
Printed in U.S.A. August, 1993




PCM56U pdf, 반도체, 판매, 대치품
DISCUSSION OF
SPECIFICATIONS
The PCM56 is specified to provide critical performance
criteria for a wide variety of applications. The most critical
specifications for D/A converter in audio applications are
Total Harmonic Distortion, Differential Linearity Error,
Bipolar Zero Error, parameter shifts with time and
temperature, and settling time effects on accuracy.
The PCM56 is factory-trimmed and tested for all critical key
specifications.
The accuracy of a D/A converter is described by the transfer
function shown in Figure 1. Digital input to analog output
relationship is shown in Table I. The errors in the D/A
converter are combinations of analog errors due to the linear
circuitry, matching and tracking properties of the ladder and
scaling networks, power supply rejection, and reference
errors. In summary, these errors consist of initial errors
including Gain, Offset, Linearity, Differential Linearity, and
Power Supply Sensitivity. Gain drift over temperature rotates
the line (Figure 1) about the bipolar zero point and Offset
drift shifts the line left or right over the operating temperature
range. Most of the Offset and Gain drift with temperature or
time is due to the drift of the internal reference zener diode.
The converter is designed so that these drifts are in opposite
directions. This way the Bipolar Zero voltage is virtually
unaffected by variations in the reference voltage.
DIGITAL INPUT CODES
The PCM56 accepts serial input data (MSB first) in the
Binary Two’s Complement (BTC) form. Refer to Table I
for input/output relationships.
DIGITAL INPUT
ANALOG OUTPUT
Binary Two’s
Complement (BTC)
7FFF Hex
8000 Hex
0000 Hex
FFFF Hex
DAC Output
+ Full Scale
– Full Scale
Bipolar Zero
Zero –1LSB
Voltage (V),
VOUT Mode
+2.999908
–3.000000
0.000000
–0.000092
Current (mA),
IOUT Mode
–0.999970
+1.000000
0.000000
+0.030500µA
TABLE I. Digital Input to Analog Output Relationship.
BIPOLAR ZERO ERROR
Initial Bipolar Zero Error (Bit 1 “on” and all other bits “off”)
is the deviation from 0V out and is factory-trimmed to
typically ±30mV at +25°C.
DIFFERENTIAL LINEARITY ERROR
Differential Linearity Error (DLE) is the deviation from an
ideal 1LSB change from one adjacent output state to the
next. DLE is important in audio applications because
excessive DLE at Bipolar Zero (at the “major carry”) can
result in audible crossover distortion for low level output
signals. Initial DLE on the PCM56 is factory trimmed to
typically ±0.001% of FSR. The MSB DLE is adjustable to
zero using the circuit shown in Figure 6.
0111...1111
0111...1110
0000...0010
0000...0001
0000...0000
1111...1111
1111...1110
1000...0001
1000...0000
All Bits On
Gain
Drift
Offset
Drift
Bipolar
Zero
–FSR/2
Analog Output
* See Table I for digital code definitions.
(+FSR/2) –1LSB
FIGURE 1. Input vs Output for an Ideal Bipolar D/A Con-
verter.
POWER SUPPLY SENSITIVITY
Changes in the DC power supplies will affect accuracy.
The PCM56 power supply sensitivity is shown by Figure 2.
Normally, regulated power supplies with 1% or less ripple
are recommended for use with the DAC. See also Power
Supply Connections paragraph in the Installation and
Operating Instructions section.
SETTLING TIME
Settling time is the total time (including slew time) required
for the output to settle within an error band around its final
value after a change in input (see Figure 3).
Settling times are specified to ±0.006% of FSR: one for a
large output voltage change of 6V and one for a 1LSB
change. The 1LSB change is measured at the major carry
(0000 hex to ffff hex), the point at which the worst-case
settling time occurs.
86
80
74
68
62
56
52
46
40
34
28
1
Negative Supplies
Positive Supplies
10 100 1k
Frequency (Hz)
FIGURE 2. Power Supply Sensitivity.
10k 100k
®
PCM56
4

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PCM56U 전자부품, 판매, 대치품
Clock
(1)
MSB
LSB
Data (2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2
MSB
Latch
Enable
(3)
(4)
NOTES: (1) If clock is stopped between input of 16-bit data words, latch enable (LE) must remain low until after the first clock of the next 16-bit data
word stream. (2) Data format is binary two's complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch
enable (LE) must remain low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going
negative.
FIGURE 7. Input Timing Diagram.
Data
Input
Clock
Input
> 40ns
LSB
>15ns >15ns
> 40ns
> 40ns
> 100ns
> 5ns
MSB
Latch
Enable
> One Clock Cycle
> 15ns
> One Clock Cycle
FIGURE 8. Input Timing Relationships.
of RF radiation or pickup is loop area; therefore, signal leads
and their return conductors should be kept close together.
This reduces the external magnetic field along with any
radiation. Also, if a signal lead and its return conductor are
wired close together, they represent a small flux-capture
cross section for any external field. This reduces radiation
pickup in the circuit.
APPLICATIONS
Figures 9 and 10 show a circuit and timing diagram for a
single PCM56 used to obtain both left- and right-channel
output in a typical digital audio system. The audio output of
the PCM56 is alternately time-shared between the left and
right channels. The design is greatly simplified because the
PCM56 is a complete D/A converter requiring no external
reference or output op amp.
A sample/hold (S/H) amplifier, or “deglitcher” is required at
the output of the D/A for both the left and right channel, as
shown in Figure 9. The S/H amplifier for the left channel is
composed of A1, SW1, and associated circuitry. A1 is used
as an integrator to hold the analog voltage in C1. Since the
source and drain of the FET switch operate at a virtual
ground when “C” and “B” are connected in the sample
mode, there is no increase in distortion caused by the
modulation effect of RON by the audio signal.
Figure 10 shows the deglitcher controls for both left and
right channels which are produced by timing control logic.
A delay of 1.5µs (tω) is provided to allow the output of the
PCM56 to settle within a small error band around its final
value before connecting it to the channel output. Due to the
fast settling time of the PCM56 it is possible to minimize the
delay between the left- and right-channel outputs when
using a single D/A converter for both channels. This is
important because the right- and left-channel data are recorded
in-phase and the use of the slower D/A converter would
result in significant phase error at higher frequencies.
The obvious solution to the phase shift problem in a two-
channel system would be to use two D/A converters (one per
channel) and time the outputs to change simultaneously.
Figure 11 shows a block diagram of the final test circuitry
used for PCM56. It should be noted that no deglitching
circuitry is required on the DAC output to meet specified
THD performance. This means that when one PCM56 is
used per channel, the need for all the sample/hold and
controls circuitry associated with a single DAC (two-channel)
design is effectively eliminated. The PCM56 is tested to
meet its THD specifications without the need for output
deglitching.
A low-pass filter is required after the PCM56 to remove all
unwanted frequency components caused by the sampling
frequency as well as those resulting from the discrete nature
of the D/A output. This filter must have a flat frequency
response over the entire audio band (0-20kHz) and a very
high attenuation above 20kHz.
Most previous digital audio circuits used a higher order (9-
13 pole) analog filter. However, the phase response of an
analog filter with these amplitude characteristics is nonlinear
and can disturb the pulse-shaped characteristic transients
contained in music.
®
7 PCM56

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