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PCM61P-P 데이터시트 PDF




Burr-Brown Corporation에서 제조한 전자 부품 PCM61P-P은 전자 산업 및 응용 분야에서
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부품번호 PCM61P-P 기능
기능 Serial Input 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER
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PCM61P-P 데이터시트, 핀배열, 회로
® PCM61P
PCM61P
Serial Input 18-Bit Monolithic Audio
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q 18-BIT MONOLITHIC AUDIO D/A
CONVERTER
q LOW MAX THD + N: –92dB Without
External Adjust
q 100% PIN COMPATIBLE WITH INDUSTRY
STD 16-BIT PCM56P
q LOW GLITCH OUTPUT OF ±3V OR ±1mA
q CAPABLE OF 8X OVERSAMPLING RATE
IN VOUT MODE
q COMPLETE WITH INTERNAL REFERENCE
AND OUTPUT OP AMP
q RELIABLE PLASTIC 16-PIN DIP PACKAGE
DESCRIPTION
The PCM61P is an 18-bit totally pin compatible per-
formance replacement for the popular 16-bit PCM56P.
With the addition of two extra bits, lower max THD+N
(–92dB; PCM61P-K) can be achieved in audio applica-
tions already using the PCM56P. The PCM61P is
complete with internal reference and output op amp and
requires no external parts to function as an 18-bit DAC.
The PCM61P is capable of an 8-times oversampling
rate (single channel) and meets all of its specifications
without an external output deglitcher.
The PCM61P comes in a small, reliable 16-pin plastic
DIP package that has passed operating life tests under
simultaneous high temperature, high humidity and high
pressure testing.
Clock
Latch Enable
Data
Control
Logic
Ref
18-Bit
IOUT DAC
Serial-To-Parallel
Shift Register
VREF
MSB Adj
RF
IOUT
SJ
_
VOUT
+
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1989 Burr-Brown Corporation
PDS-9172E
PCM61PPrinted in U.S.A. October, 1993
®




PCM61P-P pdf, 반도체, 판매, 대치품
P16 (Clock)
P18 (Data)
12 34
MSB
10 11 12 13 14 15 16 17 18
1
LSB
P17 (Latch Enable)
NOTES: (1) If clock is stopped between input of 18-bit data words, latch enable (LE) must remain low until after the first clock of the next 18-bit data word stream.
(2) Data format is binary two‘s complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch enable (LE) must remain
low at least one clock cycle after going negative. (4) Latch enable (LE) must be high for at least one clock cycle before going negative.
FIGURE 1. PCM61P Timing Diagram.
Data
Input
Clock
Input
>25ns
LSB
>15ns >15ns
>25ns
>25ns
>60ns
Latch
Enable
> One Clock Cycle
MSB
>5ns
>15ns
> One Clock Cycle
FIGURE 2. PCM61P Setup and Hold Timing Diagram.
MAXIMUM CLOCK RATE
The maximum clock rate of 16.9MHz for the PCM61P is
derived by multiplying the standard audio sample rate of
44.1kHz times sixteen (16 x oversampling) times the standard
audio word bit length of 24 (44.1kHz x 16 x 24 = 16.9MHz).
Note that this clock rate accommodates a 24-bit word length,
even though only 18 bits are actually being used.
Trim 15
470k100k200k
1 –VS
MSB Adjust 14
FIGURE 3. MSB Adjust Circuit.
MSB ERROR ADJUSTMENT PROCEDURE
(OPTIONAL)
The MSB error of the PCM61P can be adjusted to make the
differential linearity error (DLE) at BPZ essentially zero. This
is important when the signal output levels are very low,
because zero crossing noise (DLE at BPZ) becomes very
significant when compared to the small code changes occur-
ring in the LSB portion of the converter.
To statically adjust DLE at BPZ, refer to the circuit shown in
Figure 3 or the PCM61P connection diagram.
Differential linearity error at bipolar zero and THD are guar-
anteed to meet data sheet specifications without any external
adjustment. However, a provision has been made for an
optional adjustment of the MSB linearity point, which makes
it possible to eliminate DLE error at BPZ. Two procedures are
given to allow either static or dynamic adjustment. The
dynamic procedure is preferred because of the difficulty
associated with the static method (accurately measuring 16-
bit LSB steps).
After allowing ample warm-up time (5-10 minutes) to assure
stable operation of the PCM61P, select input code 3FFFF
hexadecimal (all bits on except the MSB). Measure the output
voltage using a 6-1/2 digit voltmeter and record it. Change the
digital input code to 00000 hexadecimal (all bits off except the
MSB). Adjust the 100kpotentiometer to make the output
read 22.9µV more than the voltage reading of the previous
code (a 1LSB step = 22.9µV). A much simpler method is to
dynamically adjust the DLE at BPZ. Assuming the device has
been installed in a digital audio application circuit, send the
appropriate digital input to produce a –60dB level sinusoidal
output, then adjust the 100kpotentiometer until a minimum
level of distortion is observed.
®
PCM61P
4

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부품번호상세설명 및 기능제조사
PCM61P-P

Serial Input 18-Bit Monolithic Audio DIGITAL-TO-ANALOG CONVERTER

Burr-Brown Corporation
Burr-Brown Corporation

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