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PDF 74HCT259 Data sheet ( Hoja de datos )
| Número de pieza | 74HCT259 | |
| Descripción | 8-bit addressable latch | |
| Fabricantes | Philips | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT259
8-bit addressable latch
Product specification
File under Integrated Circuits, IC06
December 1990
1 page  
Philips Semiconductors
8-bit addressable latch
Product specification
74HC/HCT259
FUNCTION TABLE
OPERATING
MODES
master reset
INPUTS
OUTPUTS
MR LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
L HXXXXL L L L L L L L
demultiplex
(active HIGH)
decoder
(when D = H)
L L d L L L Q=d L L L L L L L
L L d H L L L Q=d L L L L L L
L L d L H L L L Q=d L L L L L
L L d H H L L L L Q=d L L L L
L L d L L H L L L L Q=d L L L
L L d H L H L L L L L Q=d L L
L L d L H H L L L L L L Q=d L
L L d H H H L L L L L L L Q=d
store (do nothing) H H X X X X q0 q1 q2 q3 q4 q5 q6 q7
H L d L L L Q=d q1 q2 q3 q4 q5 q6 q7
H L d H L L q0 Q=d q2 q3 q4 q5 q6 q7
H L d L H L q0 q1 Q=d q3 q4 q5 q6 q7
H L d H H L q0 q1 q2 Q=d q4 q5 q6 q7
addressable latch
H L d L L H q0 q1 q2 q3 Q=d q5 q6 q7
H L d H L H q0 q1 q2 q3 q4 Q=d q6 q7
H L d L H H q0 q1 q2 q3 q4 q5 Q=d q7
H L d H H H q0 q1 q2 q3 q4 q5 q6 Q=d
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE transition
q = lower case letters indicate the state of the referenced output established during the last cycle in which it was
addressed or cleared
December 1990
5
5 Page 
Philips Semiconductors
8-bit addressable latch
Product specification
74HC/HCT259
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the conditional reset input (MR) to output (Qn) propagation delays.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the data set-up and hold times for the D input to LE input.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.11 Waveforms showing the address set-up and hold times for An inputs to LE input.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet 74HCT259.PDF ] | |
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