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부품번호 | 74LCX112 기능 |
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기능 | Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 8 페이지수
June 1998
Revised March 1999
74LCX112
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop
with 5V Tolerant Inputs
General Description
The LCX112 is a dual J-K flip-flop. Each flip-flop has inde-
pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q,
Q outputs. These devices are edge sensitive and change
state on the negative going transition of the clock pulse.
Clear and preset are independent of the clock and accom-
plished by a low logic level on the corresponding input.
LCX devices are designed for low voltage (3.3V or 2.5)
operation with the added capability of interfacing to a 5V
signal environment.
The 74LCX112 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs
s 2.3V–3.6V VCC specifications provided
s 7.5 ns tPD max (VCC = 3.3V), 10 µA ICC max
s Power down high impedance inputs and outputs
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 2000V
Ordering Code:
Order Number Package Number
Package Description
74LCX112M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
74LCX112SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX112MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Description
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
© 1999 Fairchild Semiconductor Corporation DS012424.prf
www.fairchildsemi.com
AC Electrical Characteristics
TA = 40°C to 85°C, RL = 500Ω
VCC = 3.3V ± 0.3V
CL=50 pF
VCC = 2.7V
CL = 50 pF
VCC = 2.5V ± 0.2V
CL=30 pF
Units
Symbol Parameters
Min Max Min Max Min Max
fMAX
Maximum Clock Frequency
150
150
150 MHz
tPHL Propagation Delay
tPLH CPn to Qn or Qn
1.5 7.5 1.5 8.0 1.5 9.0
1.5 7.5 1.5 8.0 1.5 9.0
ns
tPHL Propagation Delay
tPLH
CDn or SDn to Qn or Qn
1.5 7.0 1.5 8.0 1.5 8.4
1.5 7.0 1.7 8.0 1.5 8.4
ns
tS Setup Time
2.5 2.5 4.0 ns
tH Hold Time
1.5 1.5 2.0 ns
tW Pulse Width CP
3.3 3.3 4.0 ns
tW Pulse Width (CD, SD)
3.3 3.3 4.0 ns
tREC
Recovery Time
2.0 2.5 4.5 ns
tOSHL
tOSLH
Output to Output Skew
(Note 4)
1.0
1.0
ns
Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL), or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
Capacitance
Conditions
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL = 0V
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL = 0V
VCC
TA = 25°C
Units
(V) Typical
3.3 0.8
2.5 0.6
V
3.3 −0.8
2.5 −0.6
V
Symbol
CIN
COUT
CPD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
VCC = Open, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
Typical
7
8
25
Units
pF
pF
pF
www.fairchildsemi.com
4
4페이지 Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
7 www.fairchildsemi.com
7페이지 | |||
구 성 | 총 8 페이지수 | ||
다운로드 | [ 74LCX112.PDF 데이터시트 ] |
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74LCX112 | Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs | Fairchild Semiconductor |
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