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부품번호 | 74LCX16373MTD 기능 |
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기능 | Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 8 페이지수
February 1994
Revised April 1999
74LCX16373
Low Voltage 16-Bit Transparent Latch with 5V Tolerant
Inputs and Outputs
General Description
The LCX16373 contains sixteen non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LCX16373 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment.
The LCX16373 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V–3.6V VCC specifications provided
s 5.4 ns tPD max (VCC = 3.3V), 20 µA ICC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX16373MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCX16373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
LEn
I0–I15
O0–O15
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
© 1999 Fairchild Semiconductor Corporation DS012002.prf
www.fairchildsemi.com
DC Electrical Characteristics (Continued)
Symbol
Parameter
ICC Quiescent Supply Current
∆ICC
Increase in ICC per Input
Note 5: Outputs disabled or 3-STATE only.
Conditions
VI = VCC or GND
3.6V ≤ VI, VO ≤ 5.5V (Note 5)
VIH = VCC −0.6V
VCC
(V)
2.3 − 3.6
2.3 − 3.6
2.3 − 3.6
TA = −40°C to +85°C
Min Max
20
±20
500
Units
µA
µA
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
CL = 50 pF
VCC = 2.7V
CL = 50 pF
VCC = 2.5V ± 0.2V
CL = 30 pF
Units
Min Max Min Max Min Max
tPHL
tPLH
Propagation Delay
In to On
1.5 5.4 1.5 5.9 1.5 6.5
ns
1.5 5.4 1.5 5.9 1.5 6.5
tPHL
tPLH
Propagation Delay
LE to On
1.5 5.5 1.5 6.4 1.5 6.6
ns
1.5 5.5 1.5 6.4 1.5 6.6
tPZL
tPZH
Output Enable Time
1.5 6.1 1.5 6.5 1.5 7.9
ns
1.5 6.1 1.5 6.5 1.5 7.9
tPLZ
tPHZ
Output Disable Time
1.5 6.0 1.5 6.3 1.5 7.2
ns
1.5 6.0 1.5 6.3 1.5 7.2
tS Setup Time, In to LE
2.5 2.5 3.0 ns
tH Hold Time, In to LE
1.5 1.5 2.0 ns
tW LE Pulse Width
3.0 3.0 3.5 ns
tOSHL
tOSLH
Output to Output Skew (Note 6)
1.0
1.0
ns
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
Capacitance
Conditions
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL = 0V
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL = 0V
VCC
TA = 25°C
Units
(V) Typical
3.3 0.8
2.5 0.6
V
3.3 −0.8
2.5 −0.6
V
Symbol
CIN
COUT
CPD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
VCC = Open, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
Typical
7
8
20
Units
pF
pF
pF
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4
4페이지 Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS48A
7 www.fairchildsemi.com
7페이지 | |||
구 성 | 총 8 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
74LCX16373MTD | Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs | Fairchild Semiconductor |
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