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PDF 74LCX241SJ Data sheet ( Hoja de datos )
| Número de pieza | 74LCX241SJ | |
| Descripción | Low Voltage Octal Buffer/Line Driver with 5V Tolerant Inputs and Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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August 1998
Revised April 1999
74LCX241
Low Voltage Octal Buffer/Line Driver with
5V Tolerant Inputs and Outputs
General Description
The LCX241 is an octal buffer and line driver designed to
be employed as a memory address driver, clock driver and
bus oriented transmitter or receiver. The device is designed
for low voltage (2.5V or 3.3V) VCC applications with capa-
bility of interfacing to a 5V signal environment.
The LCX241 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s 2.3V – 3.6V VCC specifications provided
s 6.5 ns tPD max (VCC = 3.3V), 10 µA ICC max
s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human Body Model > 2000V
Machine Model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC and OE should be tied to GND through a resistor: the
minimum value or the resistor is determined by the current-sourcing capa-
bility of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX241WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LCX241MSA
M20D
20-Lead Small Outline Package (SOP), EIAJ Type II, 5.3mm Wide
74LCX241SJ
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm WIde
74LCX241MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
OE1, OE2
I0–I7
O0–O7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
© 1999 Fairchild Semiconductor Corporation DS012639.prf
www.fairchildsemi.com
1 page  
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
tPZL, tPLZ
tPZH,tPHZ
Switch
Open
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and
Disable Times for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tR = tF = 3ns)
Symbol
Vmi
Vmo
Vx
Vy
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
VCC
2.7V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
5 www.fairchildsemi.com
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