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74LCX541 데이터시트 PDF




Fairchild Semiconductor에서 제조한 전자 부품 74LCX541은 전자 산업 및 응용 분야에서
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부품번호 74LCX541 기능
기능 Low Voltage Octal Buffer/Line Driver
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74LCX541 데이터시트, 핀배열, 회로
December 2013
74LCX541
Low Voltage Octal Buffer/Line Driver
with 5V Tolerant Inputs and Outputs
Features
5V tolerant input and outputs
2.3V–3.6V VCC specifications provided
6.5ns tPD max (VCC = 3.3V), 10µA ICC max
Power-down high impedance inputs and outputs
Supports live insertion/withdrawal(1)
±24 mA output drive (VCC = 3.0V)
Implements proprietary noise/ EMI reduction circuitry
Latch-up performance exceeds JEDEC 78 conditions
ESD performance
– Human body model > 2000V
– Machine model > 200V
Leadless DQFN package
Note:
1. To ensure the high impedance state during power up
or down, OE should be tied to VCC through a pull-up
resistor: the minimum value of the resistor is
determined by the current-sourcing capability of the
driver.
General Description
The LCX541 is an octal buffer/line driver designed to be
employed as memory and address drivers, clock drivers
and bus oriented transmitter/receivers. The LCX541 is a
non inverting option of the LCX540.
This device is similar in function to the LCX244 while
providing flow-through architecture (inputs on opposite
side from outputs). This pinout arrangement makes this
device especially useful as an output port for micropro-
cessors, allowing ease of layout and greater PC board
density.
The LCX541 is designed for low voltage applications
with capability of interfacing to a 5V signal environment.
The LCX541 is fabricated with an advanced CMOS
technology to achieve high speed operation while
maintaining CMOS low power dissipation.
Ordering Information
Package
Order Number Number
Package Description
74LCX541WM
M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LCX541SJ
74LCX541BQX(2)
M20D
MLP20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 4.5mm
74LCX541MSA
MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LCX541MTC
MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Note:
2. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.1
www.fairchildsemi.com




74LCX541 pdf, 반도체, 판매, 대치품
DC Electrical Characteristics
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II
IOFF
ICC
ICC
Input Leakage Current
Power-Off Leakage Current
Quiescent Supply Current
Increase in ICC per Input
VCC (V)
2.3–2.7
2.7–3.6
2.3–2.7
2.7–3.6
2.3–3.6
2.3
2.7
3.0
2.3–3.6
2.3
2.7
3.0
2.3–3.6
0
2.3–3.6
2.3–3.6
Conditions
IOH = –100µA
IOH = –8mA
IOH = –12mA
IOH = –18mA
IOH = –24mA
IOL = 100µA
IOL = 8mA
IOL = 12mA
IOL = 16mA
IOL = 24mA
0 VI 5.5V
VI or VO = 5.5V
VI = VCC or GND
3.6V VI, VO 5.5V(5)
VIH = VCC = 0.6V
TA = –40°C to +85°C
Min.
Max.
1.7
2.0
0.7
0.8
VCC – 0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
±5.0
10
10
±10
500
Units
V
V
V
V
µA
µA
µA
µA
AC Electrical Characteristics
Symbol
tPHL, tPLH
tPZL, tPZH
tPLZ, tPHZ
tOSHL, tOSLH
Parameter
Propagation Delay
Output Enable Time
Output Disable Time
Output to Output Skew(6)
TA = –40°C to +85°C, RL = 500
VCC = 3.3V ± 0.3V,
CL = 50pF
VCC = 2.7V,
CL = 50pF
VCC = 2.5V ± 0.2V,
CL = 30pF
Min. Max. Min. Max. Min. Max. Units
1.5 6.5 1.5 7.5 1.5 7.8 ns
1.5 8.5 1.5 9.5 1.5 10.5 ns
1.5 7.5 1.5 8.5 1.5 9.0 ns
1.0 ns
Notes
5. Outputs disabled or 3-STATE only.
6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two
separate outputs of the same device. The specification applies to any outputs switching in the same direction,
either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.1
4
www.fairchildsemi.com

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74LCX541 전자부품, 판매, 대치품
Schematic Diagram (Generic for LCX Family)
Input Stage
P1
Data
ESD
D2 N+/P–
N1
Input Stage
P2
N2
P4
P3
Enable
ESD
D4 N+/P–
N3
N4
VCC
P5 X1
VDD
GTO™
Output
D6
N+/P–
N5
©2006 Fairchild Semiconductor Corporation
74LCX541 Rev. 1.6.1
7
www.fairchildsemi.com

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74LCX540

Low Voltage Octal Buffer/Line Driver

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74LCX541

Low Voltage Octal Buffer/Line Driver

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