PDF 74LCX543WM Data sheet ( Hoja de datos )

Número de pieza	74LCX543WM
Descripción	Low Voltage Octal Registered Transceiver with 5V Tolerant Inputs and Outputs
Fabricantes	Fairchild Semiconductor
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No Preview Available ! May 1995 Revised April 1999 74LCX543 Low Voltage Octal Registered Transceiver with 5V Tolerant Inputs and Outputs General Description The LCX543 is a non-inverting octal transceiver containing two sets of D-type registers for temporary storage of data flowing in either direction. Separate Latch Enable and Out- put Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. The LCX543 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. The LCX543 is fabricated with an advanced CMOS tech- nology to achieve high speed operation while maintaining CMOS low power dissipation. Features s 5V tolerant inputs and outputs s 2.3V − 3.6V VCC specifications provided s 7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s ±24 mA Output Drive (VCC = 3.0V) s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74LCX543WM 74LCX543MSA 74LCX543MTC Package Number Package Description M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names Description OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) CEAB A-to-B Enable Input (Active LOW) CEBA B-to-A Enable Input (Active LOW) LEAB A-to-B Latch Enable Input (Active LOW) LEBA B-to-A Latch Enable Input (Active LOW) A0–A7 A-to-B Data Inputs or B-to-A 3-STATE Outputs B0–B7 B-to-A Data Inputs or A-to-B 3-STATE Outputs © 1999 Fairchild Semiconductor Corporation DS012463.prf www.fairchildsemi.com 1 page AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test tPLH, tPHL tPZL, tPLZ tPZH,tPHZ Switch Open 6V at VCC = 3.3 ± 0.3V VCC x 2 at VCC = 2.5 ± 0.2V GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic 3-STATE Output Low Enable and Disable Times for Logic trise and tfall FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tR = tF = 3ns) Symbol Vmi Vmo Vx Vy 3.3V ± 0.3V 1.5V 1.5V VOL + 0.3V VOH − 0.3V VCC 2.7V 1.5V 1.5V VOL + 0.3V VOH − 0.3V 2.5V ± 0.2V VCC/2 VCC/2 VOL + 0.15V VOH − 0.15V 5 www.fairchildsemi.com 5 Page

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