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부품번호 | 74LCX74MTC 기능 |
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기능 | Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
전체 8 페이지수
March 1995
Revised April 1999
74LCX74
Low Voltage Dual D-Type Positive
Edge-Triggered Flip-Flop with 5V Tolerant Inputs
General Description
The LCX74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. After the Clock Pulse input
threshold voltage has been passed, the Data input is
locked out and information present will not be transferred to
the outputs until the next rising edge of the Clock Pulse
input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
s 5V tolerant inputs
s 2.3V–3.6V VCC specifications provided
s 7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max
s Power down high impedance inputs and outputs
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number Package Number
Package Description
74LCX74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
74LCX74SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D1, D2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q1, Q2, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
© 1999 Fairchild Semiconductor Corporation DS012414.prf
www.fairchildsemi.com
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500Ω
Symbol
Parameter
VCC = 3.3V ± 0.3V
CL = 50 pF
VCC = 2.7V
CL = 50 pF
VCC = 2.5V ± 0.2V
CL = 30 pF
Units
Min Max Min Max Min Max
fMAX
Maximum Clock Frequency
150
150
150 MHz
tPHL Propagation Delay
tPLH CPn to Qn or Qn
1.5 7.0 1.5 8.0 1.5 8.4
1.5 7.0 1.5 8.0 1.5 8.4
ns
tPHL Propagation Delay
tPLH
CDn or SDn to Qn or Qn
1.5 7.0 1.5 8.0 1.5 8.4
1.5 7.0 1.5 8.0 1.5 8.4
ns
tS Setup Time
2.5 2.5 4.0 ns
tH Hold Time
1.5 1.5 2.0 ns
tW Pulse Width CP
3.3 3.3 4.0 ns
tW Pulse Width and CD, SD
3.3
3.6
4.0
ns
tREC
Recovery Time
2.5 3.0 4.5 ns
tOSHL
tOSLH
Output to Output Skew
(Note 4)
1.0
1.0
ns
Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLP
Quiet Output Dynamic Peak VOL
Capacitance
Conditions
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL = 0V
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 30 pF, VIH = 2.5V, VIL = 0V
VCC TA = 25°C Unit
(V) Typical
3.3 −0.8
2.5 0.6
V
3.3 −0.8
2.5 0.6
V
Symbol
CIN
COUT
CPD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
VCC = Open, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
Typical
7
8
25
Units
pF
pF
pF
www.fairchildsemi.com
4
4페이지 Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
7 www.fairchildsemi.com
7페이지 | |||
구 성 | 총 8 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
74LCX74MTC | Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs | Fairchild Semiconductor |
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