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PDF 74LCX760MTC Data sheet ( Hoja de datos )
| Número de pieza | 74LCX760MTC | |
| Descripción | Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Open Drain Outputs | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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July 2001
Revised February 2002
74LCX760
Low Voltage Buffer/Line Driver
with 5V Tolerant Inputs and Open Drain Outputs
General Description
The LCX760 is the Open Drain version of the LCX244. The
LCX760 contains eight non-inverting buffers with 3-STATE
outputs. The device may be employed as a memory
address driver, clock driver and bus-oriented transmitter/
receiver. The LCX760 is designed for low voltage (2.5V or
3.3V) VCC applications with capability of interfacing to a 5V
signal environment.
The LCX760 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s Open drain version of the LCX244
s 5V tolerant inputs and outputs
s 2.3V–3.6V VCC specifications provided
s 8.0 ns tPD max (VCC = 3.3V), 10 µA ICC max
s Power down high impedance inputs and outputs
s Supports live insertion/withdrawal (Note 1)
s 24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up conforms to JEDEC JED78
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX760WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74LCX760SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 4.4mm Wide
74LCX760MSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LCX760MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
IEEE/IEC
© 2002 Fairchild Semiconductor Corporation DS500413
www.fairchildsemi.com
1 page  
AC LOADING and WAVEFORMS
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPZL, tPLZ
Switch
6V at VCC = 3.3 ± 0.3V
VCC x 2 at VCC = 2.5 ± 0.2V
3-STATE Output Low Enable and
Disable Times for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
Symbol
Vmi
Vmo
Vx
Vy
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
VCC
2.7V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
5 www.fairchildsemi.com
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet 74LCX760MTC.PDF ] | |
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