74LCXH162244 Datasheet PDF - Fairchild Semiconductor
| Part Number | 74LCXH162244 | |
| Description | Low Voltage 16-Bit Buffer/Line Driver | |
| Manufacturers | Fairchild Semiconductor | |
| Logo |  |
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September 2000
Revised May 2005
74LCXH162244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
and 26: Series Resistors in Outputs
General Description
The LCXH162244 contains sixteen non-inverting buffers
with 3-STATE outputs designed to be employed as a mem-
ory and address driver, clock driver, or bus oriented trans-
mitter/receiver. The device is nibble controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The LCXH162244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
In addition, the outputs include equivalent 26: (nominal)
series resistors to reduce overshoot and undershoot and
are designed to sink/source up to 12 mA at VCC 3.0V.
The LCXH162244 is designed for low voltage (2.5V or
3.3V) VCC applications with capability of interfacing to a 5V
signal environment.
The LCXH162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
s 5V tolerant control inputs and outputs
s 2.3V–3.6V VCC specifications provided
s Outputs include equivalent series resistance of 26: to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
s 5.3 ns tPD max (VCC 3.0V), 20 PA ICC max
s Power down high impedance inputs and outputs
s r12 mA output drive (VCC 3.0V)
s Implements proprietary noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model ! 2000V
Machine model ! 200V
Ordering Code:
Order Number Package Number
Package Description
74LCXH162244MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
74LCXH162244MEX
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LCXH162244MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
74LCXH162244MTX
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
© 2005 Fairchild Semiconductor Corporation DS500249
www.fairchildsemi.com
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DC Electrical Characteristics (Continued)
Symbol
Parameter
Conditions
II
II(HOLD)
II(OD)
Input Leakage Current
Bushold Input Minimum
Drive Hold Current
Data
Control
Bushold Input Over-Drive
Current to Change State
VI VCC or GND
0 d VI d 5.5
VIN 0.7V
VIN 1.7V
VIN 0.8V
VIN 2.0V
(Note 4)
(Note 5)
(Note 4)
(Note 5)
IOZ 3-STATE Output Leakage
0 d VO d 5.5V
VI VIH or VIL
IOFF Power-Off Leakage Current
VO 5.5V
ICC Quiescent Supply Current
VI VCC or GND
'ICC
Increase in ICC per Input
VIH VCC 0.6V
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
VCC
(V)
2.3 3.6
2.3 3.6
2.3
3.0
2.7
3.6
2.3 3.6
0
2.3 3.6
2.3 3.6
TA 40qC to 85qC
Min Max
r5.0
r5.0
45
45
75
75
300
300
450
450
r5.0
10
20
500
Units
PA
PA
PA
PA
PA
PA
PA
AC Electrical Characteristics
TA 40qC to 85qC, RL 500 :
Symbol
Parameter
VCC 3.3V r 0.3V
CL 50 pF
VCC 2.7V
CL 50 pF
VCC 2.5V r 0.2V
CL 30 pF
Units
Min Max Min Max Min Max
tPHL Propagation Delay
tPLH Data to Output
1.0 5.3 1.0 6.0 1.0 6.4
1.0 5.3 1.0 6.0 1.0 6.4
ns
tPZL
tPZH
Output Enable Time
1.0 6.3 1.0 7.1 1.0 8.2
1.0 6.3 1.0 7.1 1.0 8.2
ns
tPLZ
tPHZ
Output Disable Time
1.0 5.4 1.0 5.7 1.0 6.5
1.0 5.4 1.0 5.7 1.0 6.5
ns
tOSHL
tOSLH
Output to Output Skew (Note 6)
1.0
1.0
ns
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
Quiet Output Dynamic Peak VOL
VOLV
Quiet Output Dynamic Valley VOL
Capacitance
Conditions
CL 50 pF, VIH 3.3V, VIL 0V
CL 30 pF, VIH 2.5V, VIL 0V
CL 50 pF, VIH 3.3V, VIL 0V
CL 30 pF, VIH 2.5V, VIL 0V
VCC
TA 25qC
Units
(V) Typical
3.3 0.35
V
2.5 0.25
3.3 0.35
2.5 0.25
V
Symbol
CIN
COUT
CPD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
VCC Open, VI 0V or VCC
VCC 3.3V, VI 0V or VCC
VCC 3.3V, VI 0V or VCC, f 10 MHz
Typical
7
8
20
Units
pF
pF
pF
5 www.fairchildsemi.com
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