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부품번호 | 74LCXH162373MEA 기능 |
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기능 | Low Voltage 16-Bit Transparent Latch with Bushold and 26 Series Resistor Outputs | ||
제조업체 | Fairchild Semiconductor | ||
로고 | |||
February 2001
Revised March 2002
74LCXH162373
Low Voltage 16-Bit Transparent Latch
with Bushold and 26Ω Series Resistor Outputs
General Description
The LCXH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LCXH162373 is designed for low voltage (2.5V or
3.3V) VCC applications with capability of interfacing to a 5V
signal environment. The 26Ω series resistor helps reduce
output overshoot and undershoot.
The LCXH162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
The LCXH162373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
Features
s 5V tolerant control inputs and outputs
s 2.3V–3.6V VCC specifications provided
s Equivalent 26Ω series resistors on outputs
s Bushold on inputs eliminates the need for external
pull-up/pull-down resistors
s 6.2 ns tPD max (VCC = 3.3V), 20 µA ICC max
s Power down high impedance inputs and outputs
s ±12 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number
Package
Number
Package Description
74LCXH162373GX
(Note 1)
BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74LCXH162373MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
74LCXH162373MEX
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LCXH162373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
74LCXH162373MTX
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: BGA package available in Tape and Reel only.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500445
www.fairchildsemi.com
Absolute Maximum Ratings(Note 2)
Symbol
Parameter
VCC Supply Voltage
VI DC Input Voltage
VO DC Output Voltage
I0 - I15
OEn, LEn
IIK DC Input Diode Current
IOK DC Output Diode Current
IO
ICC
IGND
TSTG
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
−0.5 to +7.0
−0.5 to VCC + 0.5
−0.5V to 7.0V
−0.5 to +7.0
−0.5 to VCC + 0.5
−50
−50
+50
±50
±100
±100
−65 to +150
Conditions
Output in 3-STATE
Output in HIGH or LOW State (Note 3)
VI < GND
VO < GND
VO > VCC
Units
V
V
V
mA
mA
mA
mA
mA
°C
Recommended Operating Conditions (Note 4)
Symbol
Parameter
Min Max Units
VCC Supply Voltage
Operating
Data Retention
2.0
1.5
3.6
3.6
V
VI Input Voltage
VO Output Voltage
HIGH or LOW State
3-STATE
0
0
0
VCC
VCC
5.5
V
V
IOH/IOL Output Current
VCC = 3.0V − 3.6V
±12
VCC = 2.7V − 3.0V
±8 mA
VCC = 2.3V − 2.7V
±4
TA Free-Air Operating Temperature
−40 85
°C
∆t/∆V
Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V
0 10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused control inputs must be HIGH or LOW.
DC Electrical Characteristics
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II Input Leakage Current
Conditions
IOH = −100 µA
IOH = −4 mA
IOH = −4 mA
IOH = −6 mA
IOH = −8 mA
IOH = −12 mA
IOL = 100 µA
IOL = 4 mA
IOL = 4 mA
IOL = 6 mA
IOL = 8 mA
IOL = 12 mA
VI = VCC or GND
VCC
(V)
2.3 − 2.7
2.7 − 3.6
2.3 − 2.7
2.7 − 3.6
2.3 − 3.6
2.3
2.7
3.0
2.7
3.0
2.3 − 3.6
2.3
2.7
3.0
2.7
3.0
2.3 − 3.6
TA = −40°C to +85°C
Min Max
1.7
2.0
0.7
0.8
VCC − 0.2
1.8
2.2
2.4
2.0
2.0
0.2
0.6
0.4
0.55
0.6
0.8
±5.0
Units
V
V
V
V
µA
www.fairchildsemi.com
4
4페이지 AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
Switch
Open
6V at VCC = 3.3 ± 0.3V, and 2.7V
VCC x 2 at VCC = 2.5 ± 0.2V
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and
Disable Times for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Characteristics; f = 1 MHz, tr = tf = 3 ns)
Symbol
Vmi
Vmo
Vx
Vy
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
VCC
2.7V
1.5V
1.5V
VOL + 0.3V
VOH − 0.3V
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH − 0.15V
7 www.fairchildsemi.com
7페이지 | |||
구 성 | 총 11 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
74LCXH162373MEA | Low Voltage 16-Bit Transparent Latch with Bushold and 26 Series Resistor Outputs | Fairchild Semiconductor |
74LCXH162373MEX | Low Voltage 16-Bit Transparent Latch with Bushold and 26 Series Resistor Outputs | Fairchild Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |