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74LCXH16373MEA 데이터시트 PDF




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부품번호 74LCXH16373MEA 기능
기능 Low Voltage 16-Bit Transparent Latch with Bushold
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74LCXH16373MEA 데이터시트, 핀배열, 회로
February 2001
Revised August 2001
74LCXH16373
Low Voltage 16-Bit Transparent Latch with Bushold
General Description
The LCXH16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LCXH16373 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment.
The LCXH16373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
The LCXH16373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data input at a valid logic level.
Features
I 5V tolerant control inputs and outputs
I 2.3V–3.6V VCC specifications provided
I 5.4 ns tPD max (VCC = 3.3V), 20 µA ICC max
I Bushold on inputs eliminates the need for external
pull-up/pull-down resistors
I Power down high impedance outputs
I ±24 mA output drive (VCC = 3.0V)
I Implements patented noise/EMI reduction circuitry
I Latch-up performance exceeds 500 mA
I ESD performance:
Human body model > 2000V
Machine model > 200V
I Also available in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number Package Number
Package Description
74LCXH16373GX
(Note 1)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74LCXH16373MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCXH16373MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: BGA package available in Tape and Reel only.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500440
www.fairchildsemi.com




74LCXH16373MEA pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings(Note 3)
Symbol
VCC
VI
VO
IIK
IOK
IO
ICC
IGND
TSTG
Parameter
Value
Conditions
Supply Voltage
0.5 to +7.0
DC Input Voltage
DC Output Voltage
I0 - I15 0.5 to VCC + 0.5
OEn, LEn 0.5V to 7.0V
0.5 to +7.0 Output in 3-STATE
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
0.5 to VCC + 0.5 Output in HIGH or LOW State (Note 4)
50 VI < GND
50 VO < GND
+50 VO > VCC
±50
DC Supply Current per Supply Pin
±100
DC Ground Current per Ground Pin
±100
Storage Temperature
65 to +150
Units
V
V
V
mA
mA
mA
mA
mA
°C
Recommended Operating Conditions (Note 5)
Symbol
Parameter
Min Max Units
VCC Supply Voltage
Operating
Data Retention
2.0
1.5
3.6
3.6
V
VI Input Voltage
VO Output Voltage
HIGH or LOW State
3-STATE
0
0
0
VCC
VCC
5.5
V
V
IOH/IOL Output Current
VCC = 3.0V 3.6V
±24
VCC = 2.7V 3.0V
±12 mA
VCC = 2.3V 2.7V
±8
TA Free-Air Operating Temperature
40 85
°C
t/V
Input Edge Rate, VIN = 0.8V2.0V, VCC = 3.0V
0 10 ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recom-
mended Operating Conditionstable will define the conditions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Floating or unused control inputs must be HIGH or LOW.
DC Electrical Characteristics
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II Input Leakage Current
Conditions
IOH = −100 µA
IOH = 8 mA
IOH = −12 mA
IOH = −18 mA
IOH = −24 mA
IOL = 100 µA
IOL = 8 mA
IOL = 12 mA
IOL = 16 mA
IOL = 24 mA
VI = VCC or GND
VCC
(V)
2.3 2.7
2.7 3.6
2.3 2.7
2.7 3.6
2.3 3.6
2.3
2.7
3.0
3.0
2.3 3.6
2.3
2.7
3.0
3.0
2.3 3.6
TA = −40°C to +85°C
Min Max
1.7
2.0
0.7
0.8
VCC 0.2
1.8
2.2
2.4
2.2
0.2
0.6
0.4
0.4
0.55
±5.0
Units
V
V
V
V
µA
www.fairchildsemi.com
4

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74LCXH16373MEA 전자부품, 판매, 대치품
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
tPZL, tPLZ
tPZH,tPHZ
Switch
Open
6V at VCC = 3.3 ± 0.3V, and 2.7V
VCC x 2 at VCC = 2.5 ± 0.2V
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and
Disable Times for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
Symbol
Vmi
Vmo
Vx
Vy
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH 0.3V
VCC
2.7V
1.5V
1.5V
VOL + 0.3V
VOH 0.3V
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH 0.15V
7 www.fairchildsemi.com

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74LCXH16373MEA

Low Voltage 16-Bit Transparent Latch with Bushold

Fairchild Semiconductor
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