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74LCXZ16240 데이터시트 PDF




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부품번호 74LCXZ16240 기능
기능 Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs (Preliminary)
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74LCXZ16240 데이터시트, 핀배열, 회로
Preliminary
February 2000
Revised February 2000
74LCXZ16240
Low Voltage 16-Bit Inverting Buffer/Line Driver with
5V Tolerant Inputs/Outputs (Preliminary)
General Description
The LCXZ16240 contains sixteen inverting buffers with 3-
STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is nibble controlled. Each nibble has
separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
When VCC is between 0 and 1.5V, the LCXZ16240 is in the
high impedance state during power up or power down. This
places the outputs in the high impedance (Z) state prevent-
ing intermittent low impedance loading or glitching in bus
oriented applications.
The LCXZ16240 is designed for low voltage (2.7V or 3.3V)
VCC applications with capacity of interfacing to a 5V signal
environment.
The LCXZ16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
s 5V tolerant inputs and outputs
s Guaranteed power up/down high impedance
s Supports live insertion/withdrawal
s 2.7V–3.6V VCC specifications provided
s 4.5 ns tPD max (VCC = 3.3V), 20 µA ICC max
s ±24 mA output drive (VCC = 3.0V)
s Implements patented noise/EMI reduction circuitry
s Latch-up performance exceeds 500 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Order Number Package Number
Package Description
74LCXZ16240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCXZ16240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Symbol
Pin Descriptions
Pin Names
OEn
I0–I15
O0–O15
Description
Output Enable Inputs (Active LOW)
Inputs
Outputs
© 2000 Fairchild Semiconductor Corporation DS500257
www.fairchildsemi.com




74LCXZ16240 pdf, 반도체, 판매, 대치품
Preliminary
AC Electrical Characteristics
TA = −40°C to +85°C, RL = 500
Symbol
Parameter
VCC = 3.3V ± 0.3V
CL = 50 pF
VCC = 2.7V
CL = 50 pF
Units
Min Max Min Max
tPHL Propagation Delay
tPLH Data to Output
1.5 4.5 1.5 5.3
1.5 4.5 1.5 5.3
ns
tPZL
tPZH
Output Enable Time
1.5 5.4 1.5 6.0
1.5 5.4 1.5 6.0
ns
tPLZ
tPHZ
Output Disable Time
1.5 5.3 1.5 5.4
1.5 5.3 1.5 5.4
ns
tOSHL
tOSLH
Output to Output Skew (Note 5)
1.0
ns
1.0
Note 5: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
Symbol
Parameter
VOLP
VOLV
Quiet Output Dynamic Peak VOL
Quiet Output Dynamic Valley VOL
Capacitance
Conditions
CL = 50 pF, VIH = 3.3V, VIL = 0V
CL = 50 pF, VIH = 3.3V, VIL = 0V
VCC TA = 25°C Unit
(V) Typical
3.3 0.8
V
3.3 0.8
V
Symbol
CIN
COUT
CPD
Parameter
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
Conditions
VCC = Open, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC
VCC = 3.3V, VI = 0V or VCC, f = 10 MHz
Typical
7
8
20
Units
pF
pF
pF
www.fairchildsemi.com
4

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74LCXZ16240 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) unless otherwise noted
Preliminary
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS48A
7 www.fairchildsemi.com

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관련 데이터시트

부품번호상세설명 및 기능제조사
74LCXZ16240

Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs (Preliminary)

Fairchild Semiconductor
Fairchild Semiconductor
74LCXZ16240MEA

Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs (Preliminary)

Fairchild Semiconductor
Fairchild Semiconductor

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