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74LS32 데이터시트 PDF




Motorola Semiconductors에서 제조한 전자 부품 74LS32은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 74LS32 기능
기능 8-BIT SHIFT REGISTERS WITH SIGN EXTEND
제조업체 Motorola Semiconductors
로고 Motorola Semiconductors 로고


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74LS32 데이터시트, 핀배열, 회로
8-BIT SHIFT REGISTERS
WITH SIGN EXTEND
These 8-bit shift registers have multiplexed input/output data ports to
accomplish full 8-bit data handling in a single 20-pin package. Serial data may
enter the shift-right register through either D0 or D1 inputs as selected by the
data select pin. A serial output is also provided. Synchronous parallel loading
is achieved by taking the register enable and the S / P inputs low. This places
the three-state input / output ports in the data input mode. Data is entered on
the low-to-high clock transition. The data extend function repeats the sign in
the QA flip-flop during shifting. An overriding clear input clears the internal
registers when taken low whether the outputs are enabled or off. The output
enable does not affect synchronous operation of the register.
Multiplexed Inputs/ Outputs Provide Improved Bit Density
Sign Extend Function
Direct Overriding Clear
3-State Outputs Drive Bus Lines Directly
(TOP VIEW)
DATA SIGN
VCC SELECT EXTEND D1
20 19 18 17
B/QB D/QD F/QF H/QH
16 15 14 13
Q/H CLOCK
12 11
DS SE D1 B/QB D/QD F/QF H/GH Q/H
G CK
S/P D0 A/QA C/QC E/QE G/QG OE CLR
12
REGISTER S/P
ENABLE
3 4 5 6 7 8 9 10
D0 A/QA C/QC E/QE G/QG OUTPUT CLEAR GND
ENABLE
GUARANTEED OPERATING RANGES
Symbol
Parameter
VCC
Supply Voltage
TA Operating Ambient Temperature Range
IOH
Output Current — High
QH
IOL
Output Current — Low
QH
QH
IOH
Output Current — High
QA– QH
QA– QH
IOL
Output Current — Low
QA– QH
QA– QH
54
74
54
74
54, 74
54
74
54
74
54
74
SN54/74LS322A
8-BIT SHIFT REGISTERS
WITH SIGN EXTEND
LOW POWER SCHOTTKY
20
1
20
1
20
1
J SUFFIX
CERAMIC
CASE 732-03
N SUFFIX
PLASTIC
CASE 738-03
DW SUFFIX
SOIC
CASE 751D-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
Min Typ Max Unit
4.5 5.0 5.5
4.75 5.0 5.25
V
– 55 25 125 °C
0 25 70
– 0.4
mA
4.0 mA
8.0
– 1.0
– 2.6
mA
12 mA
24
FAST AND LS TTL DATA
5-1




74LS32 pdf, 반도체, 판매, 대치품
SN54 / 74LS322A
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
Maximum Clock Frequency
25 35
tPHL
tPLH
Propagation Delay, Clock
to QH
26 35
22 33
tPHL
Propagation Delay, Clear
to QH
27 35
tPHL
tPLH
Propagation Delay, Clock
to QA– QH
22 33
16 25
tPHL
Propagation Delay, Clear
to QA– QH
22 35
tPZH
tPZL
Output Enable Time
15 35
15 35
tPHZ
tPLZ
Output Disable Time
15 25
15 25
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Symbol
tW
tW
tW
ts
ts
th
th
trec
Parameter
Clock Pulse Width HIGH
Clock Pulse Width LOW
Clear Pulse Width LOW
Data Setup Time
Select Setup Time
Data Hold Time
Select Hold Time
Recovery Time
Min
25
15
20
20
15
0
10
20
Limits
Typ
Max
Unit
MHz
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions
CL = 15 pF
CL = 45 pF,
RL = 667
CL = 5.0 pF
Test Conditions
VCC = 5.0 V
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH Data to the Q outputs.
FAST AND LS TTL DATA
5-4

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