Datasheet.kr   

74LV109 데이터시트 PDF




Philips에서 제조한 전자 부품 74LV109은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 74LV109 자료 제공

부품번호 74LV109 기능
기능 Dual JK flip-flop with set and reset; positive-edge trigger
제조업체 Philips
로고 Philips 로고


74LV109 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 12 페이지수

미리보기를 사용할 수 없습니다

74LV109 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
74LV109
Dual JK flip-flop with set and reset;
positive-edge trigger
Product specification
Supersedes data of 1997 Jun 06
IC24 Data Handbook
1998 Apr 20
Philips
Semiconductors




74LV109 pdf, 반도체, 판매, 대치품
Philips Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger
Product specification
74LV109
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING MODES
nSD nRD nCP
nJ
nK
nQ
nQ
Asynchronous set
L
H
X
X
X
H
L
Asynchronous reset
H
L
X
X
X
L
H
Undetermined
L L XXXHH
Toggle
HHh l q
Load “0” (reset)
HH
l
lL
Load “1” (set)
HHh hH
Hold “no change”
H
H
l
hq
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition.
X = don’t care
= LOW-to-HIGH CP transition
q
H
L
q
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP.
MAX
UNIT
VCC
VI
VO
Tamb
DC supply voltage
Input voltage
Output voltage
Operating ambient temperature range in free air
See Note 1
See DC and AC
characteristics
1.0 3.3 3.6
V
0 – VCC V
0 – VCC V
-40
-40
+85
+125
°C
tr, tf
Input rise and fall times except for
Schmitt-trigger inputs
VCC = 1.0V to 2.0V – – 500
VCC = 2.0V to 2.7V – – 200 ns/V
VCC = 2.7V to 3.6V – – 100
NOTE:
1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
CONDITIONS
VCC
"IIK
"IOK
"IO
DC supply voltage
DC input diode current
DC output diode current
DC output source or sink current
– standard outputs
VI < –0.5 or VI > VCC + 0.5V
VO < –0.5 or VO > VCC + 0.5V
–0.5V < VO < VCC + 0.5V
RATING
–0.5 to +4.6
20
50
25
UNIT
V
mA
mA
mA
"IGND,
"ICC
DC VCC or GND current for types with
– standard outputs
50 mA
Tstg
PTOT
Storage temperature range
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
–65 to +150
750
500
400
°C
mW
NOTE:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Apr 20
4

4페이지










74LV109 전자부품, 판매, 대치품
Philips Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger
Product specification
74LV109
AC WAVEFORMS
VM = 1.5 V at VCC 2.7 V;
VM = 0.5 × VCC at VCC < 2.7 V;
VOL and VOH are the typical output voltage drop that occur with the
output load.
VI
nJ, nK
INPUT
GND
VI
nCP
INPUT
GND
VOH
nQ
OUTPUT
VOL
VOH
nQ
OUTPUT
VOL
VM
t su
th
1/f max
VM
tW
t PHL
VM
VM
t PLH
t su
th
t PLH
t PHL
The shaded areas indicate when the input is permitted to change
for predictable output performance.
SV00522
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
the clock pulse width, the nJ and nK to nCP set-up, the nCP to
nJ, nK hold times and the maximum clock pulse frequency.
TEST CIRCUIT
VCC
PULSE
GENERATOR
VI
RT
D.U.T.
VO
50pF
CL
RL = 1k
Test Circuit for switching times
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitance
RT = Termination resistance should be equal to ZOUT of pulse generators.
TEST
tPLH/tPHL
VCC
< 2.7V
2.7–3.6V
VI
VCC
2.7V
SV00901
Figure 3. Load circuitry for switching times.
Vl
nCP
INPUT
GND
Vl
nSD
INPUT
GND
Vl
nRD
INPUT
GND
VOH
nQ
OUTPUT
VOL
VOH
nQ
OUTPUT
VOL
VM
tW
tPLH
VM
tPHL
VM
VM
trem
trem
tW
VM
tPHL
tPLH
SV00523
Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ)
propagation delays, the set and reset pulse widths and the nRD,
nSD to nCP removal time.
1998 Apr 20
7

7페이지


구       성 총 12 페이지수
다운로드[ 74LV109.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
74LV10

Triple 3-input NAND gate

Philips
Philips
74LV107

Dual JK flip-flop with reset; negative-edge trigger

Philips
Philips

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵