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PDF TDA1307 Data sheet ( Hoja de datos )
| Número de pieza | TDA1307 | |
| Descripción | High-performance bitstream digital filter | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
TDA1307
High-performance bitstream digital
filter
Preliminary specification
Supersedes data of July 1993
File under Integrated Circuits, IC01
1996 Jan 08
1 page  
Philips Semiconductors
High-performance bitstream digital filter
Preliminary specification
TDA1307
PINNING
SYMBOL
WS
SCK
SD
EFAB
SBCL
PIN
1
2
3
4
5
SBDA
6
CDEC
7
VDDC3
VSSC2
DOBM
8
9
10
DSL
DSR
DSTB
CLC1
CMIC
VSSC3
CLC2
CDCC
RESYNC
POR
VDDC1
XTAL1
XTAL2
VDDOSC
VSSOSC
MODE
DOL
NDOL
VDDAL
VSSAL
VSSAR
VDDAR
DOR
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
TYPE, I/O
I
I
I
I(1)
I
I
O
O
O
O
I(2)
I
O
I
I
O
I(2)
I
O
I(2)
O
O
O
DESCRIPTION
word select input to data interface
clock input to data interface
data input to interface
error flag (active HIGH): input from decoder chip indicating unreliable data
subcode clock: a 10-bit burst clock (typ. 2.8224 MHz) input which synchronizes
the subcode data
subcode data: a 10-bit burst of data, including flags and sync bits, serially input
once per frame, clocked by burst clock input SBCL
decoder clock output: frequency division programmable by means of
pins 14 (CLC1) and 17 (CLC2) to output 192, 256, 384 or 768 times fs
positive supply 3
ground 2
digital audio output: this output contains digital audio samples which have
received interpolation, attenuation and muting plus subcode data;
transmission is in biphase-mark code
digital silence detected (active LOW) on left channel
digital silence detected (active LOW) on right channel
DOBM standby mode enforce pin (active HIGH)
application mode programming pin for CDEC (pin 7) frequency division
clock output, provided to be used as running clock by microprocessor
(in master mode only), output 96fs
ground 3
application mode programming pin for CDEC (pin 7) frequency division
master / slave mode selection pin
resynchronization: out-of-lock indication from data input section (active HIGH)
power-on reset (active LOW)
supply voltage 1
crystal oscillator terminal: local crystal oscillator sense forced input in slave mode
crystal oscillator output: drive output to crystal
positive supply connection to crystal oscillator circuitry
ground connection to crystal oscillator circuitry
evaluation mode programming pin (active LOW); in normal operation, this pin
should be left open-circuit or connected to the positive supply
data output left channel to bitstream DAC TDA1547
complementary data output left channel to TDA1547 in double differential mode
positive supply connection to output data driving circuitry, left channel
ground connection to output data driving circuitry, left channel
ground connection to output data driving circuitry, right channel
positive supply connection to output data driving circuitry, right channel
data output right channel to TDA1547
1996 Jan 08
5
5 Page 
Philips Semiconductors
High-performance bitstream digital filter
Preliminary specification
TDA1307
Table 2 Microprocessor control register file
ADDRESS
A3 A2
00
00
01
01
BANK
A1 A0
B0 B1
00X X
010 1
10
11
000 1
10
11
100 1
10
11
D3
BANK B0
FCON
FSS7
FSS3
DCEN
FN7
FN3
DEMC1
INS1
RES2
D2
BANK B1
DIT
FSS6
FSS2
DCSH
FN6
FN2
DEMC0
INS0
NS
D1
ATT
FSS9
FSS5
FSS1
FN9
FN5
FN1
RES0
FS1
RST
D0
DIM
FSS8
FSS4
FSS0
FN8
FN4
FN0
RES1
FS0
STBY
INITIAL STATE
0011
0000
0010
1000
0111
0000
1101
0000
0000
1000
Following is a list of the programming values for the
various control words in the register file. Information on the
meaning of the different controls can be found under the
sections covering the corresponding signal processing
blocks (see sections “Multiple format input interface” to
“Third and fourth order noise shaping”).
BANK B0, BANK B1
Programming of the bank bits is given in Table 2. The bank
bits can be changed by addressing register location 0000.
Subsequent addressing will result in access of locations
according to the last selected bank.
DIT
Dither control bit: logic 1 to activate dither addition, logic 0
deactivates.
FSS9 to FSS0
Fade function 10-bit control value to program fade speed,
in number of samples per fade step.
DCEN
DC-filter enable bit: logic 1 enables subtraction of the
DC-level from the input signal, logic 0 disables.
ATT
Attenuation control bit: logic 1 to activate −12 dB
attenuation, logic 0 to deactivate. As the attenuate control
bit shares a control word with the bank bits, ATT has to be
refreshed each time a new bank is selected.
DCSH
DC-filter sample or hold control bit: when DCSH = 0 the
DC-level of the input signal is continuously evaluated.
When DCSH = 1 the once acquired DC value, to be
subtracted from the input signal, is held constant.
DIM
Digital mute control bit: logic 1 to activate mute, logic 0 to
deactivate. An active digital mute will override the
attenuation function. As with ATT, DIM needs to be
refreshed with each change in bank selection.
FCON
Fade function control bit: logic 1 to activate the fade
function, logic 0 to deactivate.
FN9 to FN0
Fade function 10-bit control value to program volume level.
DEMC1, DEMC0
De-emphasis function enable and fs selection bits.
1996 Jan 08
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA1307.PDF ] | |
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