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부품번호 | TDA1314 기능 |
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기능 | Quadruple filter DAC | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
Philips Semiconductors
Quadruple filter DAC
Product specification
TDA1314T
FEATURES
• High dynamic range to enable digital DSP (Digital Signal
Processor) volume control
• 18 bits data input format for each of the four channels
• Four times bit-serial oversampling filter
• 1st-order 4fas (audio sampling frequency) noise shaper
• Four very low noise DACs
• Only 1st-order analog post filtering required
• Smooth power-on of the DAC output currents
• Because of the automatic digital PLL divider range
setting the master clock is selectable in a wide 4fas
integer range
• Insensitive to jitter on the I2S-bus signals with respect to
the DAC total harmonic distortion deterioration.
APPLICATIONS
• Stand-alone quadruple low noise DAC
• Car radio DAC in conjunction with DSP.
GENERAL DESCRIPTION
The TDA1314T is a quadruple very low noise high
dynamic range DAC which is intended for use in motor
cars and is controlled by the car radio DSP. Each channel
incorporates an 8th-order IIR up-sampling filter from 1ASF
to 4ASF followed by a 1st-order noise shaper and DAC.
The DAC currents are converted to audio voltage signals
using operational amplifiers (one per channel).
QUICK REFERENCE DATA
Vref = 2.5 and 5 V; Tamb = 25 °C; all voltages referenced to ground; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
VDDA
VDDD
IO(DAC)
VO(DAC)
RES
(THD + N)/S
DR
DS
Ptot
Tamb
analog supply voltage
digital supply voltage
DAC output current (FS)
DAC output voltage,
nominal DAC operational
amplifier output voltage
DAC resolution
total harmonic distortion
plus noise-to-signal ratio
dynamic range of DAC
digital silence
total power dissipation
operating ambient
temperature
Rref = 20.5 kΩ
RL ≥ 5 kΩ; Rfb = 3 kΩ
4.5
4.5
±0.4
1.0
length of data input word
fi = 1 kHz;
0 dB signal level
fi = 1 kHz;
−60 dB signal level
no signal; A-weighted
−
−
92
−
−
−40
5.0
5.0
±0.5
−
−
−66
96
−110
85
+25
MAX.
5.5
5.5
±0.6
4.0
18
−56
−
−100
−
+85
UNIT
V
V
mA
V
bits
dB
dB
dB
mW
°C
ORDERING INFORMATION
TYPE NUMBER
TDA1314T
NAME
SO28
PACKAGE
DESCRIPTION
plastic small outline package; 28 leads; body width 7.5 mm
VERSION
SOT136-1
August 1994
2
Philips Semiconductors
Quadruple filter DAC
Fig.2 Pin configuration.
Product specification
TDA1314T
FUNCTIONAL DESCRIPTION
I2S-bus interface
The word select input (pin 26) is connected to the word
select line of the I2S-bus interface. This interface has
a standard I2S-bus specification as described in the
Philips “I2S-bus specification” (ordering number
9398 332 10011). Figure 4 shows an excerpt of the Philips
I2S-bus specification interface report with respect to the
general timing and format of the I2S-bus. WS logic 0
means left channel word, logic 1 means right
channel word.
The serial clock input (pin 4) must be in accordance with
the I2S-bus specification, i.e. a continuous clock.
Serial data front (SDF, pin 25) and serial data rear (SDR,
pin 24) are the I2S-bus serial data lines to be processed in
the DACs for the loudspeakers of the car (see Fig.2, blocks
DACFL and DACFR for the front loudspeakers and blocks
DACRL and DACRR for the right loudspeakers). FL stands
for Front Left, FR for Front Right, RL for Rear Left and RR
for Rear Right. In order to utilize the capabilities of this IC
fully, the data word length should be 18 bits. Signals
derived from this block are 4 × 18-bit parallel data words
which are applied to the 4fs up-sample filters.
4ASF generator
SYNTHESIZER
SELINPH (pin 3) and WS (pin 26) are the data inputs for
this block which generates the FASFDAC, this being the
4fas signal (at 4 times the audio sample frequency), which
is used to latch the data words to the DACs and as a
reference to the clock generator block for the up-sample
filters. It consists of a digital PLL operating at the master
clock signal MCLK (pin 5). In normal mode (i.e. in the
event that the MCLK signal on pin 5 is a jitter free clock,
with a frequency of integer multiples between 45 and 128,
of 4 times the frequency of the WS signal) this block is able
to generate a jitter free FASFDAC signal for optimum
performance of the DAC. This mode is called the free
running mode.
If, in some applications, there is considerable jitter on the
MCLK while WS is more stable (less jitter), the
phase-locked mode should be selected. This mode is
normally not used and is not recommended.
August 1994
5
4페이지 Philips Semiconductors
Quadruple filter DAC
Product specification
TDA1314T
Fig.4 Total harmonic distortion plus noise-to-signal ratio as a function of output volume.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VDDD
VDDA
VDDO
Vn
Txtal
Tstg
Tamb
Ves
PARAMETER
digital supply voltage
analog supply voltage
operational amplifier supply voltage
voltage on any other pin
crystal temperature
storage temperature
operating ambient temperature
electrostatic handling
CONDITIONS
note 1
note 1
note 1
note 2
MIN.
0
0
0
0
−
−55
−40
−2 000
Notes
1. All voltages (pins 6, 7 and 15) referenced to ground.
2. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
MAX.
6.0
6.0
6.0
VDD
+150
+150
+85
+2 000
UNIT
V
V
V
V
°C
°C
°C
V
THERMAL CHARACTERISTICS
SYMBOL
Rth j-a
PARAMETER
thermal resistance from junction to ambient in free air
VALUE
76
UNIT
K/W
August 1994
8
7페이지 | |||
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |