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PDF TDA1318 Data sheet ( Hoja de datos )
| Número de pieza | TDA1318 | |
| Descripción | DCC read amplifier | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA1318
DCC read amplifier
Preliminary specification
File under Integrated Circuits, IC01
Philips Semiconductors
April 1996
1 page  
Philips Semiconductors
DCC read amplifier
Preliminary specification
TDA1318
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
DCC data amplifiers
For DCC operation the TDA1318 has eight channels for
the main data and one channel for the auxiliary data. The
eight main data channels have low-noise preamplifiers,
pre-equalisation for frequencies from 1 kHz to 50 kHz
(1st order high-pass filter, −3 dB point 75 kHz) and
low-pass filtering for anti-aliasing (2nd order active, −3 dB
point 120 kHz). The auxiliary channel has a preamplifier
with a flat frequency response. A continuous output
(OUTX) is available for this channel. All inputs are
differential and must be AC-coupled to the MRHs. The
inputs are internally biased by V14.
Automatic gain control
The DCC part is equipped with an AGC circuit which
diminishes the gain of the DCC preamplifiers when the
level at output RDMUX exceeds a preset value.
In this way, an optimum voltage swing at the RDMUX
output is obtained. The response time of the AGC can be
set by an external capacitor at pin 43. There is a fixed
relation between the source and sink current at this pin.
This results in a fixed relationship between decay and
recovery time of the gain. The AGC can be switched off by
connecting pin 43 to VSS. In this condition the preamplifier
gains are maximum, as specified in Chapter
“Characteristics”.
Multiplexer
A multiplexing circuit switches the nine digital channels
sequentially to the output. The AUX data is switched to the
output buffer during two clock periods, the eight main data
channels are all sampled for one clock period. The
effective sample frequency is one tenth of the clock
frequency at RDCLK. Multiplexer timing is illustrated in
Fig.4.
April 1996
5
5 Page 
Philips Semiconductors
DCC read amplifier
Preliminary specification
TDA1318
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
∆Vn(ref)
Vo(rms)
THD
3 × standard deviation in
amplitude spread of input
referred noise
maximum output voltage
(RMS value)
total harmonic distortion
SR supply rejection
αcs channel separation
FEEDBACK AMPLIFIER
fi = 10 kHz; Rsource = 70 Ω −
fi = 1 kHz
fi = 1 kHz;
V1 = 0.5 V (RMS)
fi = 1 kHz; auxiliary data
channel; see Fig.6
fi = 1 kHz
0.5
−
−
40
0.5 −
nV√Hz
−−V
−40 −30 dB
−6 −
dB
− − dB
Io(rms)
THD
B
maximum output current
(RMS value)
total harmonic distortion
bandwidth
note 12
note 13
note 14
30 − − mA
− −60 −50 dB
50 − − kHz
Notes
1. CS = 1, SD = 1, ADR = 1; CS = 1, SD = 0, ADR = 0; CS = 1, SD = 0, ADR = 1; feedback amplifiers unloaded. The
supply pins for the feedback amplifiers are pins 28 and 29. The supply pins for all other circuits are pins 38 and 39
(see Tables 1 and 2).
2. AGC circuit OFF (maximum gain; pin 43 connected to VSS).
3. Gain relative to gain at fi = 50 kHz. See Fig.5 for typical frequency response.
4. Difference between minimum and maximum DC level at the outputs of the data channels. To be measured at pin 1.
5. See Figs 6 and 7 for typical supply rejection.
6. Pin 2 AC-coupled to pin 3 via 100 nF capacitor.
7. Measured with a continuous sinewave of 10 kHz at pin 1, multiplexer in a fixed position. A 1 V (RMS) sinewave
corresponds with a multiplexed DCC signal of 4.3 V (p-p).
8. Periodically sampled, not tested.
9. Timing relationship between the edges of RDCLK and RDSYNC is illustrated in Fig.3. Figure 4 illustrates the action
of the multiplexer switches.
10. The output current can be adjusted by connecting a resistor between the adjust pin and VSS. A 68 Ω resistor will
produce 10 mA (typ.) through the MRHs (see Fig.9).
11. A resistor of 210 Ω connected between sense current output and VDD; frequency range from 10 kHz to 100 kHz;
sense current = 10 mA; pin 7 decoupled to VSS by 10 µF capacitor.
12. Closed loop; unity gain; fi = 1 kHz; THD < −45 dB; RL = 40 Ω; in accordance with Fig.10.
13. Closed loop; unity gain; fi = 1 kHz; 10 mA (RMS) output current into 40 Ω; in accordance with Fig.10.
14. Closed loop; unity gain; −3 dB bandwidth; measured in test circuit of Fig.10.
April 1996
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet TDA1318.PDF ] | |
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