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PDF TDA1388TZ Data sheet ( Hoja de datos )
| Número de pieza | TDA1388TZ | |
| Descripción | Bitstream continuous calibration filter-DAC for CD-ROM audio applications | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA1388T
Bitstream continuous calibration
filter-DAC for CD-ROM audio
applications
Objective specification
File under Integrated Circuits, IC01
1995 Dec 08
1 page  
Philips Semiconductors
Bitstream continuous calibration filter-DAC
for CD-ROM audio applications
Objective specification
TDA1388T
PINNING
SYMBOL PIN
DESCRIPTION
VSSO
HPOUTL
1 operational amplifier ground
2 left headphone output voltage
HPINL
3 left headphone input voltage
VOL
FILTCL
Vref
IF1
4 left channel audio voltage output
5 capacitor for left channel 1st-order
filter function, should be connected
between this pin and VOL (pin 4)
6 internal reference voltage
7 input format selection 1
IF2 8 input format selection 2
BCK
9 bit clock input
WS 10 word selection input
DATA
11 data input
VDDD
VSSD
SYSCLK
SYSSEL
12 digital supply voltage
13 digital ground
14 system clock 256fs or 384fs
15 system clock selection
APPL0
16 application mode 0 input
APPL1
17 application mode 1 input
APPL2
18 application mode 2 input
ACP
19 application control input
TC 20 test control
n.c. 21 not connected
VDDA
VSSA
FILTCR
VOR
HPINR
22 analog supply voltage
23 analog ground
24 capacitor for right channel 1st-order
filter function, should be connected
between this pin and VOR (pin 25)
25 right channel audio voltage output
26 right headphone input voltage
HPOUTR 27 right headphone output voltage
VDDO
28 operational amplifier supply voltage
handbook, halfpage
VSSO1 1
HPOUTL 2
28 VDDO
27 HPOUTR
HPINL 3
26 HPINR
VOL 4
FILTCL 5
25 VOR
24 FILTCR
Vref 6
IF1 7
IF2 8
BCK 9
23 VSSA
22 VDDA
TDA1388
21 VSSO2
20 TC
WS 10
19 ACP
DATA 11
18 APPL2
VDDD 12
VSSD 13
SYSCLK 14
17 APPL1
16 APPL0
15 SYSSEL
MGD014
Fig.2 Pin configuration.
1995 Dec 08
5
5 Page 
Philips Semiconductors
Bitstream continuous calibration filter-DAC
for CD-ROM audio applications
Objective specification
TDA1388T
TREBLE: a 5-bit value to program the treble setting. The used set depends on the MODE bits.
Table 14 Treble settings
TREBLE
TR4 TR3 TR2 TR1 TR0
FLAT SET (dB) MIN SET (dB) MAX SET (dB)
00000
0
0
0
00001
0
0
0
00010
0
0
0
00011
0
0
0
00100
0
2
2
00101
0
2
2
00111
0
2
2
00110
0
2
2
01001
0
4
4
01000
0
4
4
01011
0
4
4
01010
0
4
4
01101
0
6
6
01100
0
6
6
01111
0
6
6
01110
0
6
6
:::::
:
:
:
11110
0
6
6
Flat/min/max setting selection
In the TDA1388T has three setting for the digital sound
features bass boost and treble. The possible settings are
called ‘flat’, ‘min’ and ‘max’. The flat setting has no
influence on the audio signal, the minimum setting has a
small influence on the audio signal and the maximum
setting has a large influence on the audio signal. In the
static-pin mode, the flat setting is used for the bass boost
and treble filters. In the microcontroller mode, all three
settings can by controlled by a register.
Channel manipulation modes
In the TDA1388T there is a channel manipulation function
implemented. This function has a fixed value in the
static-pin mode, the left signal on the left channel and the
right signal on the right channel. In the microcontroller
mode several option are possible. The different modes are
as follows;
• Normal stereo output.
• Left/right reverse output.
• Mono left/right output: (L + R)/2.
• Output muting with soft mute.
De-emphasis
De-emphasis is controlled by an external pin in the
static-pin mode and by a register in the microcontroller
mode.The digital de-emphasis filter is dimensioned to
produce the de-emphasis frequency characteristics for the
sample rate 44.1 kHz. With its 18-bit dynamic range, the
digital de-emphasis filter of the TDA1388T is a convenient
and component saving alternative to analog de-emphasis.
De-emphasis is synchronized to the sample clock, so that
operation always takes place on complete samples.
1995 Dec 08
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet TDA1388TZ.PDF ] | |
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