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PDF TDA6500TT Data sheet ( Hoja de datos )
| Número de pieza | TDA6500TT | |
| Descripción | 5 V mixer/oscillator and synthesizer for PAL and NTSC standards | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
TDA6500TT; TDA6501TT
5 V mixer/oscillator and synthesizer
for PAL and NTSC standards
Product specification
2003 Jun 05
1 page  
Philips Semiconductors
5 V mixer/oscillator and synthesizer
for PAL and NTSC standards
Product specification
TDA6500TT; TDA6501TT
5 BLOCK DIAGRAM
handbook, full pagewidth
VCC
10 (23)
VCC
STABILIZER
VSTAB
AL0, AL1,
AL2
ATC
AGC
DETECTOR
AGC
SAW
DRIVER
(8) 25
(6) 27
(5) 28
AGC
IFFIL1
IFFIL2
(21) 12
(22) 11
IFOUT
IFGND
LBIN
RFGND
30 (3)
29 (4)
RF INPUT
LOW
P0
MHBIN1
MHBIN2
31 (2)
32 (1)
RF INPUT
MID + HIGH
P1 + P0 . P1
XTAL
14 (19)
CRYSTAL
OSCILLATOR
PLLGND
13 (20)
TDA6500TT
(TDA6501TT)
MIXER
LOW
LOW
OSCILLATOR
P0
MID
OSCILLATOR
(31) 2
(32) 1
(30) 3
(29) 4
(28) 5
LOSCOUT
LOSCIN
OSCGND
MOSCOUT
MOSCIN
MIXER
MID + HIGH
P1
HIGH
OSCILLATOR
(27) 6
(26) 7
(25) 8
(24) 9
REFERENCE
DIVIDER
64, 80, 128
fref
RSA
RSB
PHASE
COMPARATOR
CHARGE
PUMP
15-BIT
PROGRAMMABLE
DIVIDER
fdiv T0, T1, T2
CP
LOCK
DETECTOR
FL
P0 . P1
OPAMP
Vref
OS
(17) 16
(18) 15
15-BIT
FREQUENCY
REGISTER
CONTROL
REGISTER
HOSCIN1
HOSCOUT2
HOSCOUT1
HOSCIN2
CP
VT
SCL
SDA
AS
20 (13)
19 (14)
21 (12)
I2C-BUS
TRANSCEIVER
1 CP T2 T1 T0 RSA RSB OS
AUXILIARY
REGISTER
STATUS
REGISTER
POR FL AGC
POWER
ON RESET
3-BIT ADC
fref fdiv
GATE
T0, T1, T2
18 (15)
P6/ADC
The pin numbers in parenthesis represent the TDA6501TT.
ATC AL2 AL1 AL0 0 0 0 0
BAND SWITCH
REGISTER
P6
0 0 17 22 26 24 23
(16) (11) (7) (9) (10)
MCE149
P4 P3 P2 P1 P0
Fig.1 Block diagram.
2003 Jun 05
5
5 Page 
Philips Semiconductors
5 V mixer/oscillator and synthesizer
for PAL and NTSC standards
Product specification
TDA6500TT; TDA6501TT
Table 9 Description of bits shown in Table 8
SYMBOL
A
MA1 and MA0
R/W
POR
FL
AGC
A2, A1 and A0
DESCRIPTION
acknowledge
programmable address bits; see Table 4
logic 1 for read mode
Power-on reset flag
POR = 0, normal operation
POR = 1, power-on state
in-lock flag
FL = 0, not locked
FL = 1, the PLL is locked
internal AGC flag
AGC = 0, internal AGC not active
AGC = 1, internal AGC is active; level below 3 V
digital output of the 5-level ADC; see Table 10
Table 10 ADC levels
VOLTAGE APPLIED TO ADC INPUT(1)
0.60VCC to VCC
0.45VCC to 0.60VCC
0.30VCC to 0.45VCC
0.15VCC to 0.30VCC
0 to 0.15VCC
Note
1. Accuracy is ±0.03VCC.
A2 A1 A0
100
011
010
001
000
7.3 Power-on reset
The Power-on detection threshold voltage (VPOR) is set to VCC = 3.5 V at room temperature. Below this threshold, the
device is reset to the Power-on state.
In the Power-on state, the charge pump current is set to 280 µA, the tuning voltage output is disabled, the test bits T2, T1
and T0 are set to 001, the AGC take-over point is set to 112 dBµV and the AGC current is set to the slow mode. The high
band is selected by default.
Table 11 Default bits at Power-on reset
BIT
NAME
BYTE
MSB
LSB
Address byte
ADB
1
1
0
0
0
MA1
MA0
X
Divider byte 1 DB1 0 X X X X X X X
Divider byte 2 DB2 X X X X X X X X
Control byte
CB 1 1 0 0 1 X X 1
Band switch byte BB
−
0
−
0
0
0
0
0
Auxiliary byte
AB 0
0
1
0
−
−
−
−
2003 Jun 05
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA6500TT.PDF ] | |
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