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PDF AM29LV128L Data sheet ( Hoja de datos )

Número de pieza AM29LV128L
Descripción 128 Megabit (8 M x 16-Bit/16 M x 8-Bit) MirrorBit 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O Control
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Am29LV128MH/L
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 25270 Revision C Amendment +2 Issue Date September 9, 2003

1 page




AM29LV128L pdf
DATASHEET
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations ....................................................... 9
Word/Byte Configuration .......................................................... 9
VersatileIO™ (VIO) Control ....................................................... 9
Requirements for Reading Array Data ................................... 10
Page Mode Read ............................................................................10
Writing Commands/Command Sequences ............................ 10
Write Buffer .....................................................................................10
Accelerated Program Operation ......................................................10
Autoselect Functions .......................................................................10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Sector Address Table........................................................ 12
Autoselect Mode ..................................................................... 18
Table 3. Autoselect Codes, (High Voltage Method) ....................... 18
Sector Group Protection and Unprotection ............................. 19
Table 4. Sector Group Protection/Unprotection Address Table ..... 19
Write Protect (WP#) ................................................................ 20
Temporary Sector Group Unprotect ....................................... 20
Figure 1. Temporary Sector Group Unprotect Operation ................20
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...21
SecSi (Secured Silicon) Sector Flash Memory Region .......... 22
Table 5. SecSi Sector Contents ...................................................... 22
Figure 3. SecSi Sector Protect Verify ..............................................23
Hardware Data Protection ...................................................... 23
Low VCC Write Inhibit .....................................................................23
Write Pulse “Glitch” Protection ........................................................23
Logical Inhibit ..................................................................................23
Power-Up Write Inhibit ....................................................................23
Common Flash Memory Interface (CFI) . . . . . . . 23
Table 6. CFI Query Identification String ..........................................24
Table 7. System Interface String..................................................... 24
Table 8. Device Geometry Definition ..............................................25
Table 9. Primary Vendor-Specific Extended Query ........................26
Command Definitions . . . . . . . . . . . . . . . . . . . . . 27
Reading Array Data ................................................................ 27
Reset Command ..................................................................... 27
Autoselect Command Sequence ............................................ 27
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 28
Word/Byte Program Command Sequence ............................. 28
Unlock Bypass Command Sequence ..............................................28
Write Buffer Programming ...............................................................28
Accelerated Program ......................................................................29
Figure 4. Write Buffer Programming Operation ...............................30
Figure 5. Program Operation ..........................................................31
Program Suspend/Program Resume Command Sequence ... 31
Figure 6. Program Suspend/Program Resume ...............................32
Chip Erase Command Sequence ........................................... 32
Sector Erase Command Sequence ........................................ 32
Figure 7. Erase Operation ...............................................................33
Erase Suspend/Erase Resume Commands ........................... 33
Command Definitions ............................................................. 34
Table 10. Command Definitions (x16 Mode, BYTE# = VIH) ........... 34
Table 11. Command Definitions (x8 Mode, BYTE# = VIL).............. 35
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 36
DQ7: Data# Polling ................................................................. 36
Figure 8. Data# Polling Algorithm .................................................. 36
RY/BY#: Ready/Busy# ............................................................ 37
DQ6: Toggle Bit I .................................................................... 37
Figure 9. Toggle Bit Algorithm ........................................................ 38
DQ2: Toggle Bit II ................................................................... 38
Reading Toggle Bits DQ6/DQ2 ............................................... 38
DQ5: Exceeded Timing Limits ................................................ 39
DQ3: Sector Erase Timer ....................................................... 39
DQ1: Write-to-Buffer Abort ..................................................... 39
Table 12. Write Operation Status................................................... 40
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 41
Figure 10. Maximum Negative Overshoot Waveform ................... 41
Figure 11. Maximum Positive Overshoot Waveform ..................... 41
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 41
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. Test Setup .................................................................... 43
Table 13. Test Specifications ......................................................... 43
Key to Switching Waveforms. . . . . . . . . . . . . . . . 43
Figure 13. Input Waveforms and Measurement Levels ................. 43
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44
Read-Only Operations ........................................................... 44
Figure 14. Read Operation Timings ............................................... 44
Figure 15. Page Read Timings ...................................................... 45
Hardware Reset (RESET#) .................................................... 46
Figure 16. Reset Timings ............................................................... 46
Erase and Program Operations .............................................. 47
Figure 17. Reset Timings ............................................................... 48
Figure 18. Program Operation Timings .......................................... 49
Figure 19. Accelerated Program Timing Diagram .......................... 49
Figure 20. Chip/Sector Erase Operation Timings .......................... 50
Figure 21. Data# Polling Timings (During Embedded Algorithms) . 51
Figure 22. Toggle Bit Timings (During Embedded Algorithms) ...... 52
Figure 23. DQ2 vs. DQ6 ................................................................. 52
Temporary Sector Group Unprotect ....................................... 53
Figure 24. Temporary Sector Group Unprotect Timing Diagram ... 53
Figure 25. Sector Group Protect and Unprotect Timing Diagram .. 54
Alternate CE# Controlled Erase and Program Operations ..... 55
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings .......................................................................... 56
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 56
Erase And Programming Performance. . . . . . . . 57
TSOP Pin and BGA Package Capacitance . . . . . 58
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 59
TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline
Package (TSOP) ..................................................................... 59
LAA064—64-Ball Fortified Ball Grid Array
13 x 11 mm Package .............................................................. 60
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 61
September 9, 2003
Am29LV128MH/L
3

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AM29LV128L arduino
DATASHEET
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Device Bus Operations
DQ8–DQ15
Operation
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
CE# OE# WE# RESET# WP# ACC
L LH
H
XX
L HL
H (Note 3) X
L HL
H (Note 3) VHH
VCC ±
0.3 V
X
X
VCC ±
0.3 V
X
H
L HH
H
XX
X XX
L
XX
Addresses
(Note 2)
AIN
AIN
AIN
DQ0– BYTE#
DQ7
= VIH
BYTE#
= VIL
DOUT
DOUT
(Note 4) (Note 4)
(Note 4) (Note 4)
DQ8–DQ14
= High-Z,
DQ15 = A-1
X High-Z High-Z High-Z
X High-Z High-Z High-Z
X High-Z High-Z High-Z
Sector Group Protect
(Note 2)
L HL
VID
H
SA, A6 =L,
X A3=L, A2=L, (Note 4) X
A1=H, A0=L
X
Sector Group Unprotect
(Note 2)
L
H
L
VID
H
SA, A6=H,
X A3=L, A2=L, (Note 4) X
A1=H, A0=L
X
Temporary Sector Group
Unprotect
X
X
X
VID
H
X
AIN (Note 4) (Note 4) High-Z
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A22:A0 in word mode; A22:A-1 in byte mode. Sector addresses are A22:A15 in both modes.
2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See the
“Sector Group Protection and Unprotection” section.
3. If WP# = VIL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as
determined by the method described in “Write Protect (WP#)”. All sectors are unprotected when shipped from the factory (The
SecSi Sector may be factory protected depending on version ordered.)
4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
VersatileIO™ (VIO) Control
The VersatileIO™ (VIO) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on VIO. See Ordering Information
for VIO options on this device.
September 9, 2003
Am29LV128MH/L
9

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