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PDF APW6020 Data sheet ( Hoja de datos )
| Número de pieza | APW6020 | |
| Descripción | Advanced Dual PWM and Dual Linear Power Controllers | |
| Fabricantes | Etc | |
| Logotipo |  |
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APW6020
Advanced Dual PWM and Dual Linear Power Controllers
Features
General Description
• 4 Regulated Voltages are provided
− Microprocessor Core (1.3V to 3.5V)
− AGP Bus (1.5V or 3.3V)
− Memory (1.8V) , GTL Bus (1.5V)
• Simple Single-Loop Control Designs
Voltage-Mode PWM Control
• Fast PWM Converter Transient Response
High-Bandwidth Error Amplifiers
− Full 0% to 100% Duty Ratios
• Excellent Output Voltage Regulation
− Core PWM Output : ± 1% Over Temperature
− Other Outputs : ± 3% Over Temperature
• TTL-Compatible 5- Bit DAC Microprocessor
Core Output Voltage Selection
−
Wide
Range
-
1.3V
DC
to
3.5
V
DC
• Power-Good Output Voltage Monitor
• Over-Voltage and Over-Current Fault Monitors
• Small Converter Size
− Constant Frequency Operation
− 200kHz Free-Running Oscillator ; Program-
mable From 50kHz to Over 800kHz
− Small External Component Count
Applications
The APW6020 provides the power control and pro-
tection for four output voltages in high-performance ,
graphics intensive microprocessor and computer
applications. The IC integrates two voltage-mode
PWM controllers and two linear controllers , as well
as the monitoring and protection functions into a single
package. One PWM controller regulates the micro-
processor core voltage with a synchronous-rectified
buck converter. The second PWM controller sup-
plies the computer’s AGP 1.5V or 3.3V bus power
with a standard Buck converter. The linear control-
lers requlate the power for the 1.5V GTL bus , and
the 1.8V power for the North/South Bridge core volt-
age and/or cache memory circuits. The APW6020
includes an Intel-compatible , TTL 5-input digital-to-
analog converter (DAC) that adjusts the core PWM
output voltage from 1.3 VDC to 2.05 VDC in 0.05V steps
and from 2.1 V to 3.5 V in 0.1V increments. The
DC DC
precision reference and voltage-mode control provide
±1% static regulation. The second PWM controller’s
output is user-selectable , through a TTL-compatible
signal applied at the SELECT pin , for levels of 1.5V
or 3.3V with ±3% accuracy. The two linear regula-
tors provide fixed output
) and 1.8V±3% (VOUT4 ).
voltages
of
1.5V±
3%
(VOUT3
The APW6020 monitors all the output voltages. A
single Power Good signal is issued when the core is
within ±10% of the DAC setting and all other outputs
are above their under-voltage levels. Additional built-
in over-voltage protection for the core output uses
the lower MOSFET to prevent output voltages above
115% of the DAC setting. The PWM controller’s over-
current function monitors the output current by using
the voltage drop across the upper MOSFET’s r .
DS(ON)
• Motherboard Power Regulation for Computers
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ANPEC Electronics Corp.
Rev. A.2 - May, 2001
1
www.anpec.com.tw
1 page  
APW6020
Functional Pin Description
UGATE2 (Pin 1)
VSEN2 (Pin 10)
Connect UGATE2 pin to the standard BUCK PWM
converter’s MOSFET gate. This pin provides the gate
drive for the MOSFET.
PHASE2 (Pin 2)
Connect this pin to the output of the standard Buck
PWM converter. The voltage at this pin is regulated
to the level predetermined by the logic-level status of
the SELECT pin. This pin is also monitored by the
PGOOD comparator circuit.
Connect the PHASE2 pin to the standard BUCK PWM
converter’s MOSFET source. This pin is used to
monitor the voltage drop across the MOSFET for
over-current protection.
VID0 , VID1 , VID2 , VID3 , VID4 (Pins 7, 6 , 5 , 4 and
3)
VID0-4 are the TTL-compatible input pins to the 5-bit
DAC. The logic states of these five pins program the
internal voltage reference (DACOUT). The level of
DACOUT sets the microprocessor core converter
output voltage , as well as the coresponding PGOOD
and OVP thresholds.
SELECT (Pin 11)
This pin determines the output voltage of the AGP
bus switching regulator. A low TTL input sets the
output voltage to 1.5V , while a high input sets the
output voltage to 3.3V.
SS (Pin 12)
Connect a capacitor from this pin to ground. This
capacitor , along with an internal 28µA current source
, sets the soft-start interval of the converter.
FAULT / RT (Pin 13)
PGOOD (Pin 8)
PGOOD is an open drain output used to indicate the
status of the output voltages. This pin is pulled low
when the synchronous regulator output is not within
10% of the DACOUT reference voltage or when any
of the other outputs are below their under-voltage
thresholds.
The PGOOD output is open for ‘11111’ VID code.
This pin provides oscillator switching frequency
adjustment. By placing a resistor (RT ) from this pin
to GND , the nominal 200kHz switching frequency is
increased. Conversely , connecting a pull-up resis-
tor (RT ) from this pin to VCC reduces the switching
frequency.
Nominally , the voltage at this pin is 1.26V. In the
event of an over-voltage or over-current condition ,
this pin is internally pulled to VCC.
OCSET2 (Pin 9)
VSEN4 (Pin 14)
Connect a resistor (ROCSET ) from this pin to the drain
of the standard BUCK converter’s MOSFET. R ,
OCSET
an internal 200µA current source (IOCSET ) , and the
MOSFET’s on-resistance(rDS(ON)) set the converter
over-current (OC) trip point according to the follow-
ing equation :
I=
PEAK
IOCSET * ROCSET
r
DS(ON)
An over-current trip cycles the soft-start function.
Connect this pin to the output of the linear 1.8V
regulator. This pin is monitored for under-voltage
events.
DRIVE4 (Pin 15)
Connect this pin to the gate of an external MOSFET.
This pin provides the drive for the 1.8V regulator’s
pass transistor.
VAUX (Pin 16)
The +3.3V input voltage at this pin is monitored for
Copyright ANPEC Electronics Corp.
Rev. A.2 - May, 2001
5
www.anpec.com.tw
5 Page 
APW6020
Physical Specifications
Terminal Material
Lead Solderability
Packaging
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb)
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
1000 devices per reel
Refolw Condition (IR/ Convection or VPR Reflow)
Reference JEDEC Standard J-STD-020A APRIL 1999
Peak temperature
Pre-heat temperature
183°C
Classification Reflow Profiles
Time
Average ramp-up rate(183°C to Peak)
Preheat temperature 125 ± 25°C)
Temperature maintained above 183°C
Time within 5°C of actual peak
temperature
Peak temperature range
Ramp-down rate
Time 25°C to peak temperature
Convection or IR/ Convection
VPR
3°C/second max.
10 °C /second max.
120 seconds max.
60 ~ 150 seconds
10 ~ 20 seconds
60 seconds
220 +5/-0°C or 235 +5/-0°C
6 °C /second max.
6 minutes max.
215~ 219°C or 235 +5/-0°C
10 °C /second max.
Package Reflow Conditions
pkg. thickness ≥ 2.5mm
and all bags
Convection 220 +5/-0 °C
VPR 215-219 °C
IR/Convection 220 +5/-0 °C
pkg. thickness < 2.5mm and
pkg. volume ≥ 350 mm³
pkg. thickness < 2.5mm and pkg.
volume < 350mm³
Convection 235 +5/-0 °C
VPR 235 +5/-0 °C
IR/Convection 235 +5/-0 °C
Copyright ANPEC Electronics Corp.
Rev. A.2 - May, 2001
11
www.anpec.com.tw
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet APW6020.PDF ] | |
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